OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Diff between revs 137 and 142

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 137 Rev 142
Line 1135... Line 1135...
parameter max_burst_width_a = 4;
parameter max_burst_width_a = 4;
parameter max_burst_width_b = max_burst_width_a;
parameter max_burst_width_b = max_burst_width_a;
parameter mode = "B3";
parameter mode = "B3";
parameter memory_init = 0;
parameter memory_init = 0;
parameter memory_file = "vl_ram.v";
parameter memory_file = "vl_ram.v";
 
parameter debug = 0;
input [data_width_a-1:0] wbsa_dat_i;
input [data_width_a-1:0] wbsa_dat_i;
input [addr_width_a-1:0] wbsa_adr_i;
input [addr_width_a-1:0] wbsa_adr_i;
input [data_width_a/8-1:0] wbsa_sel_i;
input [data_width_a/8-1:0] wbsa_sel_i;
input [2:0] wbsa_cti_i;
input [2:0] wbsa_cti_i;
input [1:0] wbsa_bte_i;
input [1:0] wbsa_bte_i;
Line 1189... Line 1190...
    .clk(wbsb_clk),
    .clk(wbsb_clk),
    .rst(wbsb_rst));
    .rst(wbsb_rst));
`undef MODULE
`undef MODULE
assign we_b = wbsb_we_i & wbsb_ack_o;
assign we_b = wbsb_we_i & wbsb_ack_o;
end else if (mode=="B4") begin : b4_inst
end else if (mode=="B4") begin : b4_inst
 
assign adr_a = wbsa_adr_i;
`define MODULE dff
`define MODULE dff
`BASE`MODULE dffacka ( .d(wbsa_stb_i & wbsa_cyc_i), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
`BASE`MODULE dffacka ( .d(wbsa_stb_i & wbsa_cyc_i), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
assign wbsa_stall_o = 1'b0;
assign wbsa_stall_o = 1'b0;
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
 
assign adr_b = wbsb_adr_i;
`BASE`MODULE dffackb ( .d(wbsb_stb_i & wbsb_cyc_i), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
`BASE`MODULE dffackb ( .d(wbsb_stb_i & wbsb_cyc_i), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
`undef MODULE
`undef MODULE
assign wbsb_stall_o = 1'b0;
assign wbsb_stall_o = 1'b0;
assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;
assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;
end
end
endgenerate
endgenerate
 
 
`define MODULE dpram_be_2r2w
`define MODULE dpram_be_2r2w
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
                 .b_data_width(data_width_b),
                 .b_data_width(data_width_b),
                 .memory_init(memory_init), .memory_file(memory_file))
                 .memory_init(memory_init), .memory_file(memory_file),
 
                 .debug(debug))
`undef MODULE
`undef MODULE
ram_i (
ram_i (
    .d_a(wbsa_dat_i),
    .d_a(wbsa_dat_i),
    .q_a(wbsa_dat_o),
    .q_a(wbsa_dat_o),
    .adr_a(adr_a),
    .adr_a(adr_a),

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.