| Line 315... |
Line 315... |
input [dat_size-1:0] wbs_dat_o;
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input [dat_size-1:0] wbs_dat_o;
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input wbs_ack_o, wbs_err_o, wbs_rty_o;
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input wbs_ack_o, wbs_err_o, wbs_rty_o;
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input wb_clk, wb_rst;
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input wb_clk, wb_rst;
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wire [nr_of_ports-1:0] select;
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reg [nr_of_ports-1:0] select;
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wire [nr_of_ports-1:0] state;
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wire [nr_of_ports-1:0] state;
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wire [nr_of_ports-1:0] eoc; // end-of-cycle
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wire [nr_of_ports-1:0] eoc; // end-of-cycle
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wire [nr_of_ports-1:0] sel;
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wire [nr_of_ports-1:0] sel;
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wire idle;
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wire idle;
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| Line 332... |
Line 332... |
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wire [2:0] wbm1_cti_o, wbm0_cti_o;
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wire [2:0] wbm1_cti_o, wbm0_cti_o;
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assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
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assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
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assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : 2'b00;
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//assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
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always @ (idle or wbm_cyc_o)
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if (idle)
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casex (wbm_cyc_o)
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2'b1x : select = 2'b10;
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2'b01 : select = 2'b01;
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default : select = {nr_of_ports{1'b0}};
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endcase
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else
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select = {nr_of_ports{1'b0}};
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assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
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assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
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assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
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assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
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end
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end
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endgenerate
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endgenerate
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| Line 346... |
Line 357... |
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wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
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wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
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assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
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assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
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assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : 3'b000;
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always @ (idle or wbm_cyc_o)
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if (idle)
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casex (wbm_cyc_o)
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3'b1xx : select = 3'b100;
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3'b01x : select = 3'b010;
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3'b001 : select = 3'b001;
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default : select = {nr_of_ports{1'b0}};
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endcase
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else
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select = {nr_of_ports{1'b0}};
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// assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
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assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
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assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
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assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
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end
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endgenerate
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generate
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if (nr_of_ports == 4) begin
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wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
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assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
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//assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
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always @ (idle or wbm_cyc_o)
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if (idle)
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casex (wbm_cyc_o)
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4'b1xxx : select = 4'b1000;
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4'b01xx : select = 4'b0100;
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4'b001x : select = 4'b0010;
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4'b0001 : select = 4'b0001;
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default : select = {nr_of_ports{1'b0}};
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endcase
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else
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select = {nr_of_ports{1'b0}};
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assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
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assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
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assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
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assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
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end
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endgenerate
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generate
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if (nr_of_ports == 5) begin
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wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
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assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
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//assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
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always @ (idle or wbm_cyc_o)
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if (idle)
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casex (wbm_cyc_o)
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5'b1xxxx : select = 5'b10000;
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5'b01xxx : select = 5'b01000;
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5'b001xx : select = 5'b00100;
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5'b0001x : select = 5'b00010;
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5'b00001 : select = 5'b00001;
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default : select = {nr_of_ports{1'b0}};
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endcase
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else
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select = {nr_of_ports{1'b0}};
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assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
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assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
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assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
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assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
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assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
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assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
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assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
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assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
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end
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end
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