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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Diff between revs 60 and 61

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Line 470... Line 470...
`ifdef WB_B3_RAM_BE
`ifdef WB_B3_RAM_BE
// WB RAM with byte enable
// WB RAM with byte enable
`define MODULE wb_b3_ram_be
`define MODULE wb_b3_ram_be
module `BASE`MODULE (
module `BASE`MODULE (
`undef MODULE
`undef MODULE
    wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
    wb_dat_i, wb_adr_i, wb_cti_i, wb_bte_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
    wb_dat_o, wb_ack_o, wb_clk, wb_rst);
    wb_dat_o, wb_ack_o, wb_clk, wb_rst);
 
 
parameter nr_of_ports = 3;
parameter nr_of_ports = 3;
parameter wb_arbiter_type = 1;
parameter wb_arbiter_type = 1;
parameter adr_size = 26;
parameter adr_size = 26;
Line 490... Line 490...
localparam bw = 2 * nr_of_ports;
localparam bw = 2 * nr_of_ports;
 
 
input [dw-1:0] wb_dat_i;
input [dw-1:0] wb_dat_i;
input [aw-1:0] wb_adr_i;
input [aw-1:0] wb_adr_i;
input [cw-1:0] wb_cti_i;
input [cw-1:0] wb_cti_i;
 
input [bw-1:0] wb_bte_i;
input [sw-1:0] wb_sel_i;
input [sw-1:0] wb_sel_i;
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
output [dw-1:0] wb_dat_o;
output [dw-1:0] wb_dat_o;
reg [dw-1:0] wb_dat_o;
reg [dw-1:0] wb_dat_o;
output wb_ack_o;
output wb_ack_o;
Line 504... Line 505...
 
 
// local wb slave
// local wb slave
wire [dat_size-1:0] wbs_dat_i;
wire [dat_size-1:0] wbs_dat_i;
wire [adr_size-1:0] wbs_adr_i;
wire [adr_size-1:0] wbs_adr_i;
wire [2:0] wbs_cti_i;
wire [2:0] wbs_cti_i;
 
wire [1:0] wbs_bte_i;
wire [(dat_size/8)-1:0] wbs_sel_i;
wire [(dat_size/8)-1:0] wbs_sel_i;
wire  wbs_we_i, wbs_stb_i, wbs_cyc_i;
wire  wbs_we_i, wbs_stb_i, wbs_cyc_i;
wire [dat_size-1:0] wbs_dat_o;
wire [dat_size-1:0] wbs_dat_o;
reg wbs_ack_o;
reg wbs_ack_o;
 
 

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