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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Diff between revs 75 and 77

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Rev 75 Rev 77
Line 146... Line 146...
always @ (posedge wbs_clk or posedge wbs_rst)
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
if (wbs_rst)
        wbs_eoc <= 1'b0;
        wbs_eoc <= 1'b0;
else
else
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
                wbs_eoc <= wbs_bte_i==linear;
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_==3'b111);
        else if (wbs_eoc_alert & (a_rd | a_wr))
        else if (wbs_eoc_alert & (a_rd | a_wr))
                wbs_eoc <= 1'b1;
                wbs_eoc <= 1'b1;
 
 
`define MODULE cnt_shreg_ce_clear
`define MODULE cnt_shreg_ce_clear
`BASE`MODULE # ( .length(16))
`BASE`MODULE # ( .length(16))
Line 308... Line 308...
`define MODULE wb3avalon_bridge
`define MODULE wb3avalon_bridge
module `BASE`MODULE (
module `BASE`MODULE (
`undef MODULE
`undef MODULE
        // wishbone slave side
        // wishbone slave side
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
        // wishbone master side
        // avalon master side
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
 
 
input [31:0] wbs_dat_i;
input [31:0] wbs_dat_i;
input [31:2] wbs_adr_i;
input [31:2] wbs_adr_i;
input [3:0]  wbs_sel_i;
input [3:0]  wbs_sel_i;
Line 354... Line 354...
assign write = wbm_cyc_o & wbm_stb_o &  wbm_we_o;
assign write = wbm_cyc_o & wbm_stb_o &  wbm_we_o;
assign read  = wbm_cyc_o & wbm_stb_o & !wbm_we_o;
assign read  = wbm_cyc_o & wbm_stb_o & !wbm_we_o;
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
 
 
`define MODULE wb3wb3_bridge
`define MODULE wb3wb3_bridge
`BASE`MODULE (
`BASE`MODULE wbwb3inst (
`undef MODULE
`undef MODULE
    // wishbone slave side
    // wishbone slave side
    .wbs_dat_i(wbs_dat_i),
    .wbs_dat_i(wbs_dat_i),
    .wbs_adr_i(wbs_adr_i),
    .wbs_adr_i(wbs_adr_i),
    .wbs_sel_i(wbs_sel_i),
    .wbs_sel_i(wbs_sel_i),

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