| Line 42... |
Line 42... |
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`ifdef WB_ADR_INC
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`ifdef WB_ADR_INC
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// async wb3 - wb3 bridge
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// async wb3 - wb3 bridge
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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`define MODULE wb_adr_inc
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`define MODULE wb_adr_inc
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module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, ack_o, adr_o, clk, rst);
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module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
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`undef MODULE
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`undef MODULE
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parameter adr_width = 10;
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parameter adr_width = 10;
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parameter max_burst_width = 4;
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parameter max_burst_width = 4;
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input cyc_i, stb_i;
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input cyc_i, stb_i, we_i;
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input [2:0] cti_i;
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input [2:0] cti_i;
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input [1:0] bte_i;
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input [1:0] bte_i;
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input [adr_width-1:0] adr_i;
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input [adr_width-1:0] adr_i;
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output [adr_width-1:0] adr_o;
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output [adr_width-1:0] adr_o;
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output ack_o;
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output ack_o;
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| Line 83... |
Line 83... |
last_cycle <= (!cyc_i) ? idle :
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last_cycle <= (!cyc_i) ? idle :
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(cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? eoc :
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(cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? eoc :
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(cyc_i & !stb_i) ? ws :
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(cyc_i & !stb_i) ? ws :
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cyc;
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cyc;
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assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
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assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
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assign adr_o[max_burst_width-1:0] = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
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assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
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(last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
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adr[max_burst_width-1:0];
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assign ack_o = last_cycle == cyc;
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assign ack_o = last_cycle == cyc;
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end
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end
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endgenerate
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endgenerate
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generate
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generate
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| Line 386... |
Line 388... |
// wishbone slave side
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// wishbone slave side
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wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
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wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
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// avalon master side
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// avalon master side
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readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
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readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
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parameter linewrapburst = 1'b0;
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input [31:0] wbs_dat_i;
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input [31:0] wbs_dat_i;
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input [31:2] wbs_adr_i;
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input [31:2] wbs_adr_i;
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input [3:0] wbs_sel_i;
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input [3:0] wbs_sel_i;
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input [1:0] wbs_bte_i;
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input [1:0] wbs_bte_i;
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input [2:0] wbs_cti_i;
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input [2:0] wbs_cti_i;
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| Line 447... |
Line 451... |
if (rst) begin
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if (rst) begin
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counter <= 4'd0;
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counter <= 4'd0;
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end else
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end else
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if (wbm_we_o) begin
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if (wbm_we_o) begin
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if (!waitrequest & !last_cyc & wbm_cyc_o) begin
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if (!waitrequest & !last_cyc & wbm_cyc_o) begin
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counter <= burstcount -1;
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counter <= burstcount -4'd1;
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end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
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end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
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counter <= burstcount;
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counter <= burstcount;
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end else if (!waitrequest & wbm_stb_o) begin
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end else if (!waitrequest & wbm_stb_o) begin
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counter <= counter - 4'd1;
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counter <= counter - 4'd1;
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end
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end
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| Line 797... |
Line 801... |
`undef MODULE
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`undef MODULE
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wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
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wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
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wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
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wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
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parameter adr_size = 16;
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parameter adr_size = 16;
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parameter adr_lo = 2;
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parameter mem_size = 1<<adr_size;
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parameter mem_size = 1<<16;
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parameter dat_size = 32;
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parameter dat_size = 32;
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parameter max_burst_width = 4;
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parameter max_burst_width = 4;
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parameter memory_init = 1;
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parameter memory_init = 1;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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localparam aw = (adr_size - adr_lo);
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localparam aw = (adr_size);
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localparam dw = dat_size;
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localparam dw = dat_size;
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localparam sw = dat_size/8;
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localparam sw = dat_size/8;
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localparam cw = 3;
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localparam cw = 3;
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localparam bw = 2;
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localparam bw = 2;
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| Line 819... |
Line 822... |
input [sw-1:0] wbs_sel_i;
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input [sw-1:0] wbs_sel_i;
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input wbs_we_i, wbs_stb_i, wbs_cyc_i;
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input wbs_we_i, wbs_stb_i, wbs_cyc_i;
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output [dw-1:0] wbs_dat_o;
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output [dw-1:0] wbs_dat_o;
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output wbs_ack_o;
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output wbs_ack_o;
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input wb_clk, wb_rst;
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input wb_clk, wb_rst;
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reg wbs_ack_o;
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wire [aw-1:0] adr;
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wire [aw-1:0] adr;
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`define MODULE ram_be
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`define MODULE ram_be
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`BASE`MODULE # (
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`BASE`MODULE # (
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| Line 835... |
Line 837... |
ram0(
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ram0(
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`undef MODULE
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`undef MODULE
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.d(wbs_dat_i),
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.d(wbs_dat_i),
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.adr(adr),
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.adr(adr),
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.be(wbs_sel_i),
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.be(wbs_sel_i),
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.we(wbs_we_i),
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.we(wbs_we_i & wb_ack_o),
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.q(wbs_dat_o),
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.q(wbs_dat_o),
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.clk(wb_clk)
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.clk(wb_clk)
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);
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);
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`define MODULE wb_adr_inc
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`define MODULE wb_adr_inc
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| Line 847... |
Line 849... |
.cyc_i(wbs_cyc_i),
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.cyc_i(wbs_cyc_i),
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.stb_i(wbs_stb_i),
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.stb_i(wbs_stb_i),
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.cti_i(wbs_cti_i),
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.cti_i(wbs_cti_i),
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.bte_i(wbs_bte_i),
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.bte_i(wbs_bte_i),
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.adr_i(wbs_adr_i),
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.adr_i(wbs_adr_i),
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.we_i(wbs_we_i),
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.ack_o(wbs_ack_o),
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.ack_o(wbs_ack_o),
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.adr_o(adr),
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.adr_o(adr),
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.clk(wb_clk),
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.clk(wb_clk),
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.rst(wb_rst));
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.rst(wb_rst));
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`undef MODULE
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`undef MODULE
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