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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Diff between revs 86 and 90

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Rev 86 Rev 90
Line 55... Line 55...
output [adr_width-1:0] adr_o;
output [adr_width-1:0] adr_o;
output ack_o;
output ack_o;
input clk, rst;
input clk, rst;
 
 
reg [adr_width-1:0] adr;
reg [adr_width-1:0] adr;
 
wire [max_burst_width-1:0] to_adr;
 
 
generate
generate
if (max_burst_width==0) begin : inst_0
if (max_burst_width==0) begin : inst_0
    reg ack_o;
    reg ack_o;
    assign adr_o = adr_i;
    assign adr_o = adr_i;
Line 67... Line 68...
        ack_o <= 1'b0;
        ack_o <= 1'b0;
    else
    else
        ack_o <= cyc_i & stb_i & !ack_o;
        ack_o <= cyc_i & stb_i & !ack_o;
end else begin
end else begin
 
 
    wire [max_burst_width-1:0] to_adr;
 
 
 
    reg [1:0] last_cycle;
    reg [1:0] last_cycle;
    localparam idle = 2'b00;
    localparam idle = 2'b00;
    localparam cyc  = 2'b01;
    localparam cyc  = 2'b01;
    localparam ws   = 2'b10;
    localparam ws   = 2'b10;
    localparam eoc  = 2'b11;
    localparam eoc  = 2'b11;
Line 86... Line 85...
                      cyc;
                      cyc;
    assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
    assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
                                        (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
                                        (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
                                        adr[max_burst_width-1:0];
                                        adr[max_burst_width-1:0];
    assign ack_o = last_cycle == cyc;
    assign ack_o = (last_cycle==cyc | last_cycle==ws) & stb_i;
end
end
endgenerate
endgenerate
 
 
generate
generate
if (max_burst_width==2) begin : inst_2
if (max_burst_width==2) begin : inst_2
Line 837... Line 836...
ram0(
ram0(
`undef MODULE
`undef MODULE
    .d(wbs_dat_i),
    .d(wbs_dat_i),
    .adr(adr),
    .adr(adr),
    .be(wbs_sel_i),
    .be(wbs_sel_i),
 
    .re(wbs_stb_i),
    .we(wbs_we_i & wbs_ack_o),
    .we(wbs_we_i & wbs_ack_o),
    .q(wbs_dat_o),
    .q(wbs_dat_o),
    .clk(wb_clk)
    .clk(wb_clk)
);
);
 
 

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