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https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
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| Rev 86 |
Rev 90 |
| Line 55... |
Line 55... |
output [adr_width-1:0] adr_o;
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output [adr_width-1:0] adr_o;
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output ack_o;
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output ack_o;
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input clk, rst;
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input clk, rst;
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reg [adr_width-1:0] adr;
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reg [adr_width-1:0] adr;
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wire [max_burst_width-1:0] to_adr;
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generate
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generate
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if (max_burst_width==0) begin : inst_0
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if (max_burst_width==0) begin : inst_0
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reg ack_o;
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reg ack_o;
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assign adr_o = adr_i;
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assign adr_o = adr_i;
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| Line 67... |
Line 68... |
ack_o <= 1'b0;
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ack_o <= 1'b0;
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else
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else
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ack_o <= cyc_i & stb_i & !ack_o;
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ack_o <= cyc_i & stb_i & !ack_o;
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end else begin
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end else begin
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wire [max_burst_width-1:0] to_adr;
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reg [1:0] last_cycle;
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reg [1:0] last_cycle;
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localparam idle = 2'b00;
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localparam idle = 2'b00;
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localparam cyc = 2'b01;
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localparam cyc = 2'b01;
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localparam ws = 2'b10;
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localparam ws = 2'b10;
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localparam eoc = 2'b11;
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localparam eoc = 2'b11;
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| Line 86... |
Line 85... |
cyc;
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cyc;
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assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
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assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
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assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
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assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
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(last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
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(last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
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adr[max_burst_width-1:0];
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adr[max_burst_width-1:0];
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assign ack_o = last_cycle == cyc;
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assign ack_o = (last_cycle==cyc | last_cycle==ws) & stb_i;
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end
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end
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endgenerate
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endgenerate
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generate
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generate
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if (max_burst_width==2) begin : inst_2
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if (max_burst_width==2) begin : inst_2
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| Line 837... |
Line 836... |
ram0(
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ram0(
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`undef MODULE
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`undef MODULE
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.d(wbs_dat_i),
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.d(wbs_dat_i),
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.adr(adr),
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.adr(adr),
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.be(wbs_sel_i),
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.be(wbs_sel_i),
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.re(wbs_stb_i),
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.we(wbs_we_i & wbs_ack_o),
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.we(wbs_we_i & wbs_ack_o),
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.q(wbs_dat_o),
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.q(wbs_dat_o),
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.clk(wb_clk)
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.clk(wb_clk)
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);
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);
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