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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile library, wishbone stuff                           ////
////  Versatile library, wishbone stuff                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Wishbone compliant modules                                  ////
////  Wishbone compliant modules                                  ////
////                                                              ////
////                                                              ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   -                                                          ////
////   -                                                          ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
`ifdef WB_ADR_INC
`ifdef WB_ADR_INC
// async wb3 - wb3 bridge
// async wb3 - wb3 bridge
`timescale 1ns/1ns
`timescale 1ns/1ns
`define MODULE wb_adr_inc
`define MODULE wb_adr_inc
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
`undef MODULE
`undef MODULE
parameter adr_width = 10;
parameter adr_width = 10;
parameter max_burst_width = 4;
parameter max_burst_width = 4;
input cyc_i, stb_i, we_i;
input cyc_i, stb_i, we_i;
input [2:0] cti_i;
input [2:0] cti_i;
input [1:0] bte_i;
input [1:0] bte_i;
input [adr_width-1:0] adr_i;
input [adr_width-1:0] adr_i;
output [adr_width-1:0] adr_o;
output [adr_width-1:0] adr_o;
output ack_o;
output ack_o;
input clk, rst;
input clk, rst;
 
 
reg [adr_width-1:0] adr;
reg [adr_width-1:0] adr;
wire [max_burst_width-1:0] to_adr;
wire [max_burst_width-1:0] to_adr;
reg [max_burst_width-1:0] last_adr;
reg [max_burst_width-1:0] last_adr;
reg [1:0] last_cycle;
reg last_cycle;
localparam idle = 2'b00;
localparam idle_or_eoc = 1'b0;
localparam cyc  = 2'b01;
localparam cyc_or_ws   = 1'b1;
localparam ws   = 2'b10;
 
localparam eoc  = 2'b11;
 
 
 
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst)
if (rst)
    last_adr <= {max_burst_width{1'b0}};
    last_adr <= {max_burst_width{1'b0}};
else
else
    if (stb_i)
    if (stb_i)
        last_adr <=adr_o;
        last_adr <=adr_o[max_burst_width-1:0];
 
 
generate
generate
if (max_burst_width==0) begin : inst_0
if (max_burst_width==0) begin : inst_0
    reg ack_o;
    reg ack_o;
    assign adr_o = adr_i;
    assign adr_o = adr_i;
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        ack_o <= 1'b0;
        ack_o <= 1'b0;
    else
    else
        ack_o <= cyc_i & stb_i & !ack_o;
        ack_o <= cyc_i & stb_i & !ack_o;
end else begin
end else begin
 
 
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        last_cycle <= idle;
        last_cycle <= idle_or_eoc;
    else
    else
        last_cycle <= (!cyc_i) ? idle :
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? eoc :
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
                      (cyc_i & !stb_i) ? ws :
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
                      cyc;
                      cyc_or_ws; // cyc
    assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
                                        (!stb_i) ? last_adr :
                                        (!stb_i) ? last_adr :
                                        (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
                                        adr[max_burst_width-1:0];
                                        adr[max_burst_width-1:0];
    assign ack_o = (last_cycle==cyc | last_cycle==ws) & stb_i;
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
end
end
endgenerate
endgenerate
 
 
generate
generate
if (max_burst_width==2) begin : inst_2
if (max_burst_width==2) begin : inst_2
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        adr <= 2'h0;
        adr <= 2'h0;
    else
    else
        if (cyc_i & stb_i)
        if (cyc_i & stb_i)
            adr[1:0] <= to_adr[1:0] + 2'd1;
            adr[1:0] <= to_adr[1:0] + 2'd1;
        else
        else
            adr <= to_adr[1:0];
            adr <= to_adr[1:0];
end
end
endgenerate
endgenerate
 
 
generate
generate
if (max_burst_width==3) begin : inst_3
if (max_burst_width==3) begin : inst_3
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        adr <= 3'h0;
        adr <= 3'h0;
    else
    else
        if (cyc_i & stb_i)
        if (cyc_i & stb_i)
            case (bte_i)
            case (bte_i)
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
            endcase
            endcase
        else
        else
            adr <= to_adr[2:0];
            adr <= to_adr[2:0];
end
end
endgenerate
endgenerate
 
 
generate
generate
if (max_burst_width==4) begin : inst_4
if (max_burst_width==4) begin : inst_4
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        adr <= 4'h0;
        adr <= 4'h0;
    else
    else
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
            case (bte_i)
            case (bte_i)
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
            default: adr[3:0] <= to_adr + 4'd1;
            default: adr[3:0] <= to_adr + 4'd1;
            endcase
            endcase
        else
        else
            adr <= to_adr[3:0];
            adr <= to_adr[3:0];
end
end
endgenerate
endgenerate
 
 
generate
generate
if (adr_width > max_burst_width) begin : pass_through
if (adr_width > max_burst_width) begin : pass_through
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
end
end
endgenerate
endgenerate
 
 
endmodule
endmodule
`endif
`endif
 
 
`ifdef WB3WB3_BRIDGE
`ifdef WB3WB3_BRIDGE
// async wb3 - wb3 bridge
// async wb3 - wb3 bridge
`timescale 1ns/1ns
`timescale 1ns/1ns
`define MODULE wb3wb3_bridge
`define MODULE wb3wb3_bridge
module `BASE`MODULE (
module `BASE`MODULE (
`undef MODULE
`undef MODULE
        // wishbone slave side
        // wishbone slave side
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
        // wishbone master side
        // wishbone master side
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
 
 
input [31:0] wbs_dat_i;
input [31:0] wbs_dat_i;
input [31:2] wbs_adr_i;
input [31:2] wbs_adr_i;
input [3:0]  wbs_sel_i;
input [3:0]  wbs_sel_i;
input [1:0]  wbs_bte_i;
input [1:0]  wbs_bte_i;
input [2:0]  wbs_cti_i;
input [2:0]  wbs_cti_i;
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
output [31:0] wbs_dat_o;
output [31:0] wbs_dat_o;
output wbs_ack_o;
output wbs_ack_o;
input wbs_clk, wbs_rst;
input wbs_clk, wbs_rst;
 
 
output [31:0] wbm_dat_o;
output [31:0] wbm_dat_o;
output reg [31:2] wbm_adr_o;
output reg [31:2] wbm_adr_o;
output [3:0]  wbm_sel_o;
output [3:0]  wbm_sel_o;
output reg [1:0]  wbm_bte_o;
output reg [1:0]  wbm_bte_o;
output reg [2:0]  wbm_cti_o;
output reg [2:0]  wbm_cti_o;
output reg wbm_we_o;
output reg wbm_we_o;
output wbm_cyc_o;
output wbm_cyc_o;
output wbm_stb_o;
output wbm_stb_o;
input [31:0]  wbm_dat_i;
input [31:0]  wbm_dat_i;
input wbm_ack_i;
input wbm_ack_i;
input wbm_clk, wbm_rst;
input wbm_clk, wbm_rst;
 
 
parameter addr_width = 4;
parameter addr_width = 4;
 
 
// bte
// bte
parameter linear       = 2'b00;
parameter linear       = 2'b00;
parameter wrap4        = 2'b01;
parameter wrap4        = 2'b01;
parameter wrap8        = 2'b10;
parameter wrap8        = 2'b10;
parameter wrap16       = 2'b11;
parameter wrap16       = 2'b11;
// cti
// cti
parameter classic      = 3'b000;
parameter classic      = 3'b000;
parameter incburst     = 3'b010;
parameter incburst     = 3'b010;
parameter endofburst   = 3'b111;
parameter endofburst   = 3'b111;
 
 
parameter wbs_adr  = 1'b0;
parameter wbs_adr  = 1'b0;
parameter wbs_data = 1'b1;
parameter wbs_data = 1'b1;
 
 
parameter wbm_adr0      = 2'b00;
parameter wbm_adr0      = 2'b00;
parameter wbm_adr1      = 2'b01;
parameter wbm_adr1      = 2'b01;
parameter wbm_data      = 2'b10;
parameter wbm_data      = 2'b10;
parameter wbm_data_wait = 2'b11;
parameter wbm_data_wait = 2'b11;
 
 
reg [1:0] wbs_bte_reg;
reg [1:0] wbs_bte_reg;
reg wbs;
reg wbs;
wire wbs_eoc_alert, wbm_eoc_alert;
wire wbs_eoc_alert, wbm_eoc_alert;
reg wbs_eoc, wbm_eoc;
reg wbs_eoc, wbm_eoc;
reg [1:0] wbm;
reg [1:0] wbm;
 
 
wire [1:16] wbs_count, wbm_count;
wire [1:16] wbs_count, wbm_count;
 
 
wire [35:0] a_d, a_q, b_d, b_q;
wire [35:0] a_d, a_q, b_d, b_q;
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
reg a_rd_reg;
reg a_rd_reg;
wire b_rd_adr, b_rd_data;
wire b_rd_adr, b_rd_data;
wire b_rd_data_reg;
wire b_rd_data_reg;
wire [35:0] temp;
wire [35:0] temp;
 
 
`define WE 5
`define WE 5
`define BTE 4:3
`define BTE 4:3
`define CTI 2:0
`define CTI 2:0
 
 
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
always @ (posedge wbs_clk or posedge wbs_rst)
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
if (wbs_rst)
        wbs_eoc <= 1'b0;
        wbs_eoc <= 1'b0;
else
else
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
        else if (wbs_eoc_alert & (a_rd | a_wr))
        else if (wbs_eoc_alert & (a_rd | a_wr))
                wbs_eoc <= 1'b1;
                wbs_eoc <= 1'b1;
 
 
`define MODULE cnt_shreg_ce_clear
`define MODULE cnt_shreg_ce_clear
`BASE`MODULE # ( .length(16))
`BASE`MODULE # ( .length(16))
`undef MODULE
`undef MODULE
    cnt0 (
    cnt0 (
        .cke(wbs_ack_o),
        .cke(wbs_ack_o),
        .clear(wbs_eoc),
        .clear(wbs_eoc),
        .q(wbs_count),
        .q(wbs_count),
        .rst(wbs_rst),
        .rst(wbs_rst),
        .clk(wbs_clk));
        .clk(wbs_clk));
 
 
always @ (posedge wbs_clk or posedge wbs_rst)
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
if (wbs_rst)
        wbs <= wbs_adr;
        wbs <= wbs_adr;
else
else
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
                wbs <= wbs_data;
                wbs <= wbs_data;
        else if (wbs_eoc & wbs_ack_o)
        else if (wbs_eoc & wbs_ack_o)
                wbs <= wbs_adr;
                wbs <= wbs_adr;
 
 
// wbs FIFO
// wbs FIFO
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
              1'b0;
              1'b0;
assign a_rd = !a_fifo_empty;
assign a_rd = !a_fifo_empty;
always @ (posedge wbs_clk or posedge wbs_rst)
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
if (wbs_rst)
        a_rd_reg <= 1'b0;
        a_rd_reg <= 1'b0;
else
else
        a_rd_reg <= a_rd;
        a_rd_reg <= a_rd;
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
 
 
assign wbs_dat_o = a_q[35:4];
assign wbs_dat_o = a_q[35:4];
 
 
always @ (posedge wbs_clk or posedge wbs_rst)
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
if (wbs_rst)
        wbs_bte_reg <= 2'b00;
        wbs_bte_reg <= 2'b00;
else
else
        wbs_bte_reg <= wbs_bte_i;
        wbs_bte_reg <= wbs_bte_i;
 
 
// wbm FIFO
// wbm FIFO
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
always @ (posedge wbm_clk or posedge wbm_rst)
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
if (wbm_rst)
        wbm_eoc <= 1'b0;
        wbm_eoc <= 1'b0;
else
else
        if (wbm==wbm_adr0 & !b_fifo_empty)
        if (wbm==wbm_adr0 & !b_fifo_empty)
                wbm_eoc <= b_q[`BTE] == linear;
                wbm_eoc <= b_q[`BTE] == linear;
        else if (wbm_eoc_alert & wbm_ack_i)
        else if (wbm_eoc_alert & wbm_ack_i)
                wbm_eoc <= 1'b1;
                wbm_eoc <= 1'b1;
 
 
always @ (posedge wbm_clk or posedge wbm_rst)
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
if (wbm_rst)
        wbm <= wbm_adr0;
        wbm <= wbm_adr0;
else
else
/*
/*
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
        (wbm==wbm_adr1 & !wbm_we_o) |
        (wbm==wbm_adr1 & !wbm_we_o) |
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
*/
*/
    case (wbm)
    case (wbm)
    wbm_adr0:
    wbm_adr0:
        if (!b_fifo_empty)
        if (!b_fifo_empty)
            wbm <= wbm_adr1;
            wbm <= wbm_adr1;
    wbm_adr1:
    wbm_adr1:
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
            wbm <= wbm_data;
            wbm <= wbm_data;
    wbm_data:
    wbm_data:
        if (wbm_ack_i & wbm_eoc)
        if (wbm_ack_i & wbm_eoc)
            wbm <= wbm_adr0;
            wbm <= wbm_adr0;
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
            wbm <= wbm_data_wait;
            wbm <= wbm_data_wait;
    wbm_data_wait:
    wbm_data_wait:
        if (!b_fifo_empty)
        if (!b_fifo_empty)
            wbm <= wbm_data;
            wbm <= wbm_data;
    endcase
    endcase
 
 
assign b_d = {wbm_dat_i,4'b1111};
assign b_d = {wbm_dat_i,4'b1111};
assign b_wr = !wbm_we_o & wbm_ack_i;
assign b_wr = !wbm_we_o & wbm_ack_i;
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
                   1'b0;
                   1'b0;
assign b_rd = b_rd_adr | b_rd_data;
assign b_rd = b_rd_adr | b_rd_data;
 
 
`define MODULE dff
`define MODULE dff
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
`undef MODULE
`undef MODULE
`define MODULE dff_ce
`define MODULE dff_ce
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
`undef MODULE
`undef MODULE
 
 
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
 
 
`define MODULE cnt_shreg_ce_clear
`define MODULE cnt_shreg_ce_clear
`BASE`MODULE # ( .length(16))
`BASE`MODULE # ( .length(16))
`undef MODULE
`undef MODULE
    cnt1 (
    cnt1 (
        .cke(wbm_ack_i),
        .cke(wbm_ack_i),
        .clear(wbm_eoc),
        .clear(wbm_eoc),
        .q(wbm_count),
        .q(wbm_count),
        .rst(wbm_rst),
        .rst(wbm_rst),
        .clk(wbm_clk));
        .clk(wbm_clk));
 
 
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
assign wbm_stb_o = (wbm==wbm_data);
assign wbm_stb_o = (wbm==wbm_data);
 
 
always @ (posedge wbm_clk or posedge wbm_rst)
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
if (wbm_rst)
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
else begin
else begin
        if (wbm==wbm_adr0 & !b_fifo_empty)
        if (wbm==wbm_adr0 & !b_fifo_empty)
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
        else if (wbm_eoc_alert & wbm_ack_i)
        else if (wbm_eoc_alert & wbm_ack_i)
                wbm_cti_o <= endofburst;
                wbm_cti_o <= endofburst;
end
end
 
 
//async_fifo_dw_simplex_top
//async_fifo_dw_simplex_top
`define MODULE fifo_2r2w_async_simplex
`define MODULE fifo_2r2w_async_simplex
`BASE`MODULE
`BASE`MODULE
`undef MODULE
`undef MODULE
# ( .data_width(36), .addr_width(addr_width))
# ( .data_width(36), .addr_width(addr_width))
fifo (
fifo (
    // a side
    // a side
    .a_d(a_d),
    .a_d(a_d),
    .a_wr(a_wr),
    .a_wr(a_wr),
    .a_fifo_full(a_fifo_full),
    .a_fifo_full(a_fifo_full),
    .a_q(a_q),
    .a_q(a_q),
    .a_rd(a_rd),
    .a_rd(a_rd),
    .a_fifo_empty(a_fifo_empty),
    .a_fifo_empty(a_fifo_empty),
    .a_clk(wbs_clk),
    .a_clk(wbs_clk),
    .a_rst(wbs_rst),
    .a_rst(wbs_rst),
    // b side
    // b side
    .b_d(b_d),
    .b_d(b_d),
    .b_wr(b_wr),
    .b_wr(b_wr),
    .b_fifo_full(b_fifo_full),
    .b_fifo_full(b_fifo_full),
    .b_q(b_q),
    .b_q(b_q),
    .b_rd(b_rd),
    .b_rd(b_rd),
    .b_fifo_empty(b_fifo_empty),
    .b_fifo_empty(b_fifo_empty),
    .b_clk(wbm_clk),
    .b_clk(wbm_clk),
    .b_rst(wbm_rst)
    .b_rst(wbm_rst)
    );
    );
 
 
endmodule
endmodule
`undef WE
`undef WE
`undef BTE
`undef BTE
`undef CTI
`undef CTI
`endif
`endif
 
 
`ifdef WB3AVALON_BRIDGE
`ifdef WB3AVALON_BRIDGE
`define MODULE wb3avalon_bridge
`define MODULE wb3avalon_bridge
module `BASE`MODULE (
module `BASE`MODULE (
`undef MODULE
`undef MODULE
        // wishbone slave side
        // wishbone slave side
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
        // avalon master side
        // avalon master side
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
 
 
parameter linewrapburst = 1'b0;
parameter linewrapburst = 1'b0;
 
 
input [31:0] wbs_dat_i;
input [31:0] wbs_dat_i;
input [31:2] wbs_adr_i;
input [31:2] wbs_adr_i;
input [3:0]  wbs_sel_i;
input [3:0]  wbs_sel_i;
input [1:0]  wbs_bte_i;
input [1:0]  wbs_bte_i;
input [2:0]  wbs_cti_i;
input [2:0]  wbs_cti_i;
input wbs_we_i;
input wbs_we_i;
input wbs_cyc_i;
input wbs_cyc_i;
input wbs_stb_i;
input wbs_stb_i;
output [31:0] wbs_dat_o;
output [31:0] wbs_dat_o;
output wbs_ack_o;
output wbs_ack_o;
input wbs_clk, wbs_rst;
input wbs_clk, wbs_rst;
 
 
input [31:0] readdata;
input [31:0] readdata;
output [31:0] writedata;
output [31:0] writedata;
output [31:2] address;
output [31:2] address;
output [3:0]  be;
output [3:0]  be;
output write;
output write;
output read;
output read;
output beginbursttransfer;
output beginbursttransfer;
output [3:0] burstcount;
output [3:0] burstcount;
input readdatavalid;
input readdatavalid;
input waitrequest;
input waitrequest;
input clk;
input clk;
input rst;
input rst;
 
 
wire [1:0] wbm_bte_o;
wire [1:0] wbm_bte_o;
wire [2:0] wbm_cti_o;
wire [2:0] wbm_cti_o;
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
reg last_cyc;
reg last_cyc;
reg [3:0] counter;
reg [3:0] counter;
reg read_busy;
reg read_busy;
 
 
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst)
if (rst)
    last_cyc <= 1'b0;
    last_cyc <= 1'b0;
else
else
    last_cyc <= wbm_cyc_o;
    last_cyc <= wbm_cyc_o;
 
 
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst)
if (rst)
    read_busy <= 1'b0;
    read_busy <= 1'b0;
else
else
    if (read & !waitrequest)
    if (read & !waitrequest)
        read_busy <= 1'b1;
        read_busy <= 1'b1;
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
        read_busy <= 1'b0;
        read_busy <= 1'b0;
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
 
 
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
                    (wbm_bte_o==2'b10) ? 4'd8 :
                    (wbm_bte_o==2'b10) ? 4'd8 :
                    (wbm_bte_o==2'b11) ? 4'd16:
                    (wbm_bte_o==2'b11) ? 4'd16:
                    4'd1;
                    4'd1;
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
 
 
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst) begin
if (rst) begin
    counter <= 4'd0;
    counter <= 4'd0;
end else
end else
    if (wbm_we_o) begin
    if (wbm_we_o) begin
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
            counter <= burstcount -4'd1;
            counter <= burstcount -4'd1;
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
            counter <= burstcount;
            counter <= burstcount;
        end else if (!waitrequest & wbm_stb_o) begin
        end else if (!waitrequest & wbm_stb_o) begin
            counter <= counter - 4'd1;
            counter <= counter - 4'd1;
        end
        end
    end
    end
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
 
 
`define MODULE wb3wb3_bridge
`define MODULE wb3wb3_bridge
`BASE`MODULE wbwb3inst (
`BASE`MODULE wbwb3inst (
`undef MODULE
`undef MODULE
    // wishbone slave side
    // wishbone slave side
    .wbs_dat_i(wbs_dat_i),
    .wbs_dat_i(wbs_dat_i),
    .wbs_adr_i(wbs_adr_i),
    .wbs_adr_i(wbs_adr_i),
    .wbs_sel_i(wbs_sel_i),
    .wbs_sel_i(wbs_sel_i),
    .wbs_bte_i(wbs_bte_i),
    .wbs_bte_i(wbs_bte_i),
    .wbs_cti_i(wbs_cti_i),
    .wbs_cti_i(wbs_cti_i),
    .wbs_we_i(wbs_we_i),
    .wbs_we_i(wbs_we_i),
    .wbs_cyc_i(wbs_cyc_i),
    .wbs_cyc_i(wbs_cyc_i),
    .wbs_stb_i(wbs_stb_i),
    .wbs_stb_i(wbs_stb_i),
    .wbs_dat_o(wbs_dat_o),
    .wbs_dat_o(wbs_dat_o),
    .wbs_ack_o(wbs_ack_o),
    .wbs_ack_o(wbs_ack_o),
    .wbs_clk(wbs_clk),
    .wbs_clk(wbs_clk),
    .wbs_rst(wbs_rst),
    .wbs_rst(wbs_rst),
    // wishbone master side
    // wishbone master side
    .wbm_dat_o(writedata),
    .wbm_dat_o(writedata),
    .wbm_adr_o(address),
    .wbm_adr_o(address),
    .wbm_sel_o(be),
    .wbm_sel_o(be),
    .wbm_bte_o(wbm_bte_o),
    .wbm_bte_o(wbm_bte_o),
    .wbm_cti_o(wbm_cti_o),
    .wbm_cti_o(wbm_cti_o),
    .wbm_we_o(wbm_we_o),
    .wbm_we_o(wbm_we_o),
    .wbm_cyc_o(wbm_cyc_o),
    .wbm_cyc_o(wbm_cyc_o),
    .wbm_stb_o(wbm_stb_o),
    .wbm_stb_o(wbm_stb_o),
    .wbm_dat_i(readdata),
    .wbm_dat_i(readdata),
    .wbm_ack_i(wbm_ack_i),
    .wbm_ack_i(wbm_ack_i),
    .wbm_clk(clk),
    .wbm_clk(clk),
    .wbm_rst(rst));
    .wbm_rst(rst));
 
 
 
 
endmodule
endmodule
`endif
`endif
 
 
`ifdef WB3_ARBITER_TYPE1
`ifdef WB3_ARBITER_TYPE1
`define MODULE wb3_arbiter_type1
`define MODULE wb3_arbiter_type1
module `BASE`MODULE (
module `BASE`MODULE (
`undef MODULE
`undef MODULE
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
    wb_clk, wb_rst
    wb_clk, wb_rst
);
);
 
 
parameter nr_of_ports = 3;
parameter nr_of_ports = 3;
parameter adr_size = 26;
parameter adr_size = 26;
parameter adr_lo   = 2;
parameter adr_lo   = 2;
parameter dat_size = 32;
parameter dat_size = 32;
parameter sel_size = dat_size/8;
parameter sel_size = dat_size/8;
 
 
localparam aw = (adr_size - adr_lo) * nr_of_ports;
localparam aw = (adr_size - adr_lo) * nr_of_ports;
localparam dw = dat_size * nr_of_ports;
localparam dw = dat_size * nr_of_ports;
localparam sw = sel_size * nr_of_ports;
localparam sw = sel_size * nr_of_ports;
localparam cw = 3 * nr_of_ports;
localparam cw = 3 * nr_of_ports;
localparam bw = 2 * nr_of_ports;
localparam bw = 2 * nr_of_ports;
 
 
input  [dw-1:0] wbm_dat_o;
input  [dw-1:0] wbm_dat_o;
input  [aw-1:0] wbm_adr_o;
input  [aw-1:0] wbm_adr_o;
input  [sw-1:0] wbm_sel_o;
input  [sw-1:0] wbm_sel_o;
input  [cw-1:0] wbm_cti_o;
input  [cw-1:0] wbm_cti_o;
input  [bw-1:0] wbm_bte_o;
input  [bw-1:0] wbm_bte_o;
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
output [dw-1:0] wbm_dat_i;
output [dw-1:0] wbm_dat_i;
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
 
 
output [dat_size-1:0] wbs_dat_i;
output [dat_size-1:0] wbs_dat_i;
output [adr_size-1:adr_lo] wbs_adr_i;
output [adr_size-1:adr_lo] wbs_adr_i;
output [sel_size-1:0] wbs_sel_i;
output [sel_size-1:0] wbs_sel_i;
output [2:0] wbs_cti_i;
output [2:0] wbs_cti_i;
output [1:0] wbs_bte_i;
output [1:0] wbs_bte_i;
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
input  [dat_size-1:0] wbs_dat_o;
input  [dat_size-1:0] wbs_dat_o;
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
 
 
input wb_clk, wb_rst;
input wb_clk, wb_rst;
 
 
reg  [nr_of_ports-1:0] select;
reg  [nr_of_ports-1:0] select;
wire [nr_of_ports-1:0] state;
wire [nr_of_ports-1:0] state;
wire [nr_of_ports-1:0] eoc; // end-of-cycle
wire [nr_of_ports-1:0] eoc; // end-of-cycle
wire [nr_of_ports-1:0] sel;
wire [nr_of_ports-1:0] sel;
wire idle;
wire idle;
 
 
genvar i;
genvar i;
 
 
assign idle = !(|state);
assign idle = !(|state);
 
 
generate
generate
if (nr_of_ports == 2) begin
if (nr_of_ports == 2) begin
 
 
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
 
 
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
 
 
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
 
 
    always @ (idle or wbm_cyc_o)
    always @ (idle or wbm_cyc_o)
    if (idle)
    if (idle)
        casex (wbm_cyc_o)
        casex (wbm_cyc_o)
        2'b1x : select = 2'b10;
        2'b1x : select = 2'b10;
        2'b01 : select = 2'b01;
        2'b01 : select = 2'b01;
        default : select = {nr_of_ports{1'b0}};
        default : select = {nr_of_ports{1'b0}};
        endcase
        endcase
    else
    else
        select = {nr_of_ports{1'b0}};
        select = {nr_of_ports{1'b0}};
 
 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
 
 
end
end
endgenerate
endgenerate
 
 
generate
generate
if (nr_of_ports == 3) begin
if (nr_of_ports == 3) begin
 
 
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
 
 
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
 
 
    always @ (idle or wbm_cyc_o)
    always @ (idle or wbm_cyc_o)
    if (idle)
    if (idle)
        casex (wbm_cyc_o)
        casex (wbm_cyc_o)
        3'b1xx : select = 3'b100;
        3'b1xx : select = 3'b100;
        3'b01x : select = 3'b010;
        3'b01x : select = 3'b010;
        3'b001 : select = 3'b001;
        3'b001 : select = 3'b001;
        default : select = {nr_of_ports{1'b0}};
        default : select = {nr_of_ports{1'b0}};
        endcase
        endcase
    else
    else
        select = {nr_of_ports{1'b0}};
        select = {nr_of_ports{1'b0}};
 
 
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
 
 
end
end
endgenerate
endgenerate
 
 
generate
generate
if (nr_of_ports == 4) begin
if (nr_of_ports == 4) begin
 
 
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
 
 
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
 
 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
 
 
    always @ (idle or wbm_cyc_o)
    always @ (idle or wbm_cyc_o)
    if (idle)
    if (idle)
        casex (wbm_cyc_o)
        casex (wbm_cyc_o)
        4'b1xxx : select = 4'b1000;
        4'b1xxx : select = 4'b1000;
        4'b01xx : select = 4'b0100;
        4'b01xx : select = 4'b0100;
        4'b001x : select = 4'b0010;
        4'b001x : select = 4'b0010;
        4'b0001 : select = 4'b0001;
        4'b0001 : select = 4'b0001;
        default : select = {nr_of_ports{1'b0}};
        default : select = {nr_of_ports{1'b0}};
        endcase
        endcase
    else
    else
        select = {nr_of_ports{1'b0}};
        select = {nr_of_ports{1'b0}};
 
 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
 
 
end
end
endgenerate
endgenerate
 
 
generate
generate
if (nr_of_ports == 5) begin
if (nr_of_ports == 5) begin
 
 
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
 
 
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
 
 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
 
 
    always @ (idle or wbm_cyc_o)
    always @ (idle or wbm_cyc_o)
    if (idle)
    if (idle)
        casex (wbm_cyc_o)
        casex (wbm_cyc_o)
        5'b1xxxx : select = 5'b10000;
        5'b1xxxx : select = 5'b10000;
        5'b01xxx : select = 5'b01000;
        5'b01xxx : select = 5'b01000;
        5'b001xx : select = 5'b00100;
        5'b001xx : select = 5'b00100;
        5'b0001x : select = 5'b00010;
        5'b0001x : select = 5'b00010;
        5'b00001 : select = 5'b00001;
        5'b00001 : select = 5'b00001;
        default : select = {nr_of_ports{1'b0}};
        default : select = {nr_of_ports{1'b0}};
        endcase
        endcase
    else
    else
        select = {nr_of_ports{1'b0}};
        select = {nr_of_ports{1'b0}};
 
 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
 
 
end
end
endgenerate
endgenerate
 
 
generate
generate
if (nr_of_ports == 6) begin
if (nr_of_ports == 6) begin
 
 
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
 
 
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
 
 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
 
 
    always @ (idle or wbm_cyc_o)
    always @ (idle or wbm_cyc_o)
    if (idle)
    if (idle)
        casex (wbm_cyc_o)
        casex (wbm_cyc_o)
        6'b1xxxxx : select = 6'b100000;
        6'b1xxxxx : select = 6'b100000;
        6'b01xxxx : select = 6'b010000;
        6'b01xxxx : select = 6'b010000;
        6'b001xxx : select = 6'b001000;
        6'b001xxx : select = 6'b001000;
        6'b0001xx : select = 6'b000100;
        6'b0001xx : select = 6'b000100;
        6'b00001x : select = 6'b000010;
        6'b00001x : select = 6'b000010;
        6'b000001 : select = 6'b000001;
        6'b000001 : select = 6'b000001;
        default : select = {nr_of_ports{1'b0}};
        default : select = {nr_of_ports{1'b0}};
        endcase
        endcase
    else
    else
        select = {nr_of_ports{1'b0}};
        select = {nr_of_ports{1'b0}};
 
 
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
 
 
end
end
endgenerate
endgenerate
 
 
generate
generate
if (nr_of_ports == 7) begin
if (nr_of_ports == 7) begin
 
 
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
 
 
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
 
 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
 
 
    always @ (idle or wbm_cyc_o)
    always @ (idle or wbm_cyc_o)
    if (idle)
    if (idle)
        casex (wbm_cyc_o)
        casex (wbm_cyc_o)
        7'b1xxxxxx : select = 7'b1000000;
        7'b1xxxxxx : select = 7'b1000000;
        7'b01xxxxx : select = 7'b0100000;
        7'b01xxxxx : select = 7'b0100000;
        7'b001xxxx : select = 7'b0010000;
        7'b001xxxx : select = 7'b0010000;
        7'b0001xxx : select = 7'b0001000;
        7'b0001xxx : select = 7'b0001000;
        7'b00001xx : select = 7'b0000100;
        7'b00001xx : select = 7'b0000100;
        7'b000001x : select = 7'b0000010;
        7'b000001x : select = 7'b0000010;
        7'b0000001 : select = 7'b0000001;
        7'b0000001 : select = 7'b0000001;
        default : select = {nr_of_ports{1'b0}};
        default : select = {nr_of_ports{1'b0}};
        endcase
        endcase
    else
    else
        select = {nr_of_ports{1'b0}};
        select = {nr_of_ports{1'b0}};
 
 
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
 
 
end
end
endgenerate
endgenerate
 
 
generate
generate
if (nr_of_ports == 8) begin
if (nr_of_ports == 8) begin
 
 
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
 
 
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
 
 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
 
 
    always @ (idle or wbm_cyc_o)
    always @ (idle or wbm_cyc_o)
    if (idle)
    if (idle)
        casex (wbm_cyc_o)
        casex (wbm_cyc_o)
        8'b1xxxxxxx : select = 8'b10000000;
        8'b1xxxxxxx : select = 8'b10000000;
        8'b01xxxxxx : select = 8'b01000000;
        8'b01xxxxxx : select = 8'b01000000;
        8'b001xxxxx : select = 8'b00100000;
        8'b001xxxxx : select = 8'b00100000;
        8'b0001xxxx : select = 8'b00010000;
        8'b0001xxxx : select = 8'b00010000;
        8'b00001xxx : select = 8'b00001000;
        8'b00001xxx : select = 8'b00001000;
        8'b000001xx : select = 8'b00000100;
        8'b000001xx : select = 8'b00000100;
        8'b0000001x : select = 8'b00000010;
        8'b0000001x : select = 8'b00000010;
        8'b00000001 : select = 8'b00000001;
        8'b00000001 : select = 8'b00000001;
        default : select = {nr_of_ports{1'b0}};
        default : select = {nr_of_ports{1'b0}};
        endcase
        endcase
    else
    else
        select = {nr_of_ports{1'b0}};
        select = {nr_of_ports{1'b0}};
 
 
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
 
 
end
end
endgenerate
endgenerate
 
 
generate
generate
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
`define MODULE spr
`define MODULE spr
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
`undef MODULE
`undef MODULE
end
end
endgenerate
endgenerate
 
 
    assign sel = select | state;
    assign sel = select | state;
 
 
`define MODULE mux_andor
`define MODULE mux_andor
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
`undef MODULE
`undef MODULE
    assign wbs_cyc_i = |sel;
    assign wbs_cyc_i = |sel;
 
 
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
 
 
endmodule
endmodule
`endif
`endif
 
 
`ifdef WB_B3_RAM_BE
`ifdef WB_B3_RAM_BE
// WB RAM with byte enable
// WB RAM with byte enable
`define MODULE wb_b3_ram_be
`define MODULE wb_b3_ram_be
module `BASE`MODULE (
module `BASE`MODULE (
`undef MODULE
`undef MODULE
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
    wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
    wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
 
 
parameter adr_size = 16;
parameter adr_size = 16;
parameter mem_size = 1<<adr_size;
parameter mem_size = 1<<adr_size;
parameter dat_size = 32;
parameter dat_size = 32;
parameter max_burst_width = 4;
parameter max_burst_width = 4;
parameter memory_init = 1;
parameter memory_init = 1;
parameter memory_file = "vl_ram.vmem";
parameter memory_file = "vl_ram.vmem";
 
 
localparam aw = (adr_size);
localparam aw = (adr_size);
localparam dw = dat_size;
localparam dw = dat_size;
localparam sw = dat_size/8;
localparam sw = dat_size/8;
localparam cw = 3;
localparam cw = 3;
localparam bw = 2;
localparam bw = 2;
 
 
input [dw-1:0] wbs_dat_i;
input [dw-1:0] wbs_dat_i;
input [aw-1:0] wbs_adr_i;
input [aw-1:0] wbs_adr_i;
input [cw-1:0] wbs_cti_i;
input [cw-1:0] wbs_cti_i;
input [bw-1:0] wbs_bte_i;
input [bw-1:0] wbs_bte_i;
input [sw-1:0] wbs_sel_i;
input [sw-1:0] wbs_sel_i;
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
output [dw-1:0] wbs_dat_o;
output [dw-1:0] wbs_dat_o;
output wbs_ack_o;
output wbs_ack_o;
input wb_clk, wb_rst;
input wb_clk, wb_rst;
 
 
wire [aw-1:0] adr;
wire [aw-1:0] adr;
 
 
`define MODULE ram_be
`define MODULE ram_be
`BASE`MODULE # (
`BASE`MODULE # (
    .data_width(dat_size),
    .data_width(dat_size),
    .addr_width(aw),
    .addr_width(aw),
    .mem_size(mem_size),
    .mem_size(mem_size),
    .memory_init(memory_init),
    .memory_init(memory_init),
    .memory_file(memory_file))
    .memory_file(memory_file))
ram0(
ram0(
`undef MODULE
`undef MODULE
    .d(wbs_dat_i),
    .d(wbs_dat_i),
    .adr(adr),
    .adr(adr),
    .be(wbs_sel_i),
    .be(wbs_sel_i),
    .we(wbs_we_i & wbs_ack_o),
    .we(wbs_we_i & wbs_ack_o),
    .q(wbs_dat_o),
    .q(wbs_dat_o),
    .clk(wb_clk)
    .clk(wb_clk)
);
);
 
 
`define MODULE wb_adr_inc
`define MODULE wb_adr_inc
`BASE`MODULE # ( .adr_width(aw), .max_burst_width(max_burst_width)) adr_inc0 (
`BASE`MODULE # ( .adr_width(aw), .max_burst_width(max_burst_width)) adr_inc0 (
    .cyc_i(wbs_cyc_i),
    .cyc_i(wbs_cyc_i),
    .stb_i(wbs_stb_i),
    .stb_i(wbs_stb_i),
    .cti_i(wbs_cti_i),
    .cti_i(wbs_cti_i),
    .bte_i(wbs_bte_i),
    .bte_i(wbs_bte_i),
    .adr_i(wbs_adr_i),
    .adr_i(wbs_adr_i),
    .we_i(wbs_we_i),
    .we_i(wbs_we_i),
    .ack_o(wbs_ack_o),
    .ack_o(wbs_ack_o),
    .adr_o(adr),
    .adr_o(adr),
    .clk(wb_clk),
    .clk(wb_clk),
    .rst(wb_rst));
    .rst(wb_rst));
`undef MODULE
`undef MODULE
 
 
endmodule
endmodule
`endif
`endif
 
 
`ifdef WB_B4_RAM_BE
`ifdef WB_B4_RAM_BE
// WB RAM with byte enable
// WB RAM with byte enable
`define MODULE wb_b4_ram_be
`define MODULE wb_b4_ram_be
module `BASE`MODULE (
module `BASE`MODULE (
`undef MODULE
`undef MODULE
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
 
 
    parameter dat_width = 32;
    parameter dat_width = 32;
    parameter adr_width = 8;
    parameter adr_width = 8;
 
 
input [dat_width-1:0] wb_dat_i;
input [dat_width-1:0] wb_dat_i;
input [adr_width-1:0] wb_adr_i;
input [adr_width-1:0] wb_adr_i;
input [dat_width/8-1:0] wb_sel_i;
input [dat_width/8-1:0] wb_sel_i;
input wb_we_i, wb_stb_i, wb_cyc_i;
input wb_we_i, wb_stb_i, wb_cyc_i;
output [dat_width-1:0] wb_dat_o;
output [dat_width-1:0] wb_dat_o;
reg [dat_width-1:0] wb_dat_o;
reg [dat_width-1:0] wb_dat_o;
output wb_stall_o;
output wb_stall_o;
output wb_ack_o;
output wb_ack_o;
reg wb_ack_o;
reg wb_ack_o;
input wb_clk, wb_rst;
input wb_clk, wb_rst;
 
 
wire [dat_width/8-1:0] cke;
wire [dat_width/8-1:0] cke;
 
 
generate
generate
if (dat_width==32) begin
if (dat_width==32) begin
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
    always @ (posedge wb_clk)
    always @ (posedge wb_clk)
    begin
    begin
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
    end
    end
    always @ (posedge wb_clk or posedge wb_rst)
    always @ (posedge wb_clk or posedge wb_rst)
    begin
    begin
        if (wb_rst)
        if (wb_rst)
            wb_dat_o <= 32'h0;
            wb_dat_o <= 32'h0;
        else
        else
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
    end
    end
end
end
endgenerate
endgenerate
 
 
always @ (posedge wb_clk or posedge wb_rst)
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
if (wb_rst)
    wb_ack_o <= 1'b0;
    wb_ack_o <= 1'b0;
else
else
    wb_ack_o <= wb_stb_i & wb_cyc_i;
    wb_ack_o <= wb_stb_i & wb_cyc_i;
 
 
assign wb_stall_o = 1'b0;
assign wb_stall_o = 1'b0;
 
 
endmodule
endmodule
`endif
`endif
 
 
`ifdef WB_B4_ROM
`ifdef WB_B4_ROM
// WB ROM
// WB ROM
`define MODULE wb_b4_rom
`define MODULE wb_b4_rom
module `BASE`MODULE (
module `BASE`MODULE (
`undef MODULE
`undef MODULE
    wb_adr_i, wb_stb_i, wb_cyc_i,
    wb_adr_i, wb_stb_i, wb_cyc_i,
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
 
 
    parameter dat_width = 32;
    parameter dat_width = 32;
    parameter dat_default = 32'h15000000;
    parameter dat_default = 32'h15000000;
    parameter adr_width = 32;
    parameter adr_width = 32;
 
 
/*
/*
//E2_ifndef ROM
//E2_ifndef ROM
//E2_define ROM "rom.v"
//E2_define ROM "rom.v"
//E2_endif
//E2_endif
*/
*/
    input [adr_width-1:2]   wb_adr_i;
    input [adr_width-1:2]   wb_adr_i;
    input                   wb_stb_i;
    input                   wb_stb_i;
    input                   wb_cyc_i;
    input                   wb_cyc_i;
    output [dat_width-1:0]  wb_dat_o;
    output [dat_width-1:0]  wb_dat_o;
    reg [dat_width-1:0]     wb_dat_o;
    reg [dat_width-1:0]     wb_dat_o;
    output                  wb_ack_o;
    output                  wb_ack_o;
    reg                     wb_ack_o;
    reg                     wb_ack_o;
    output                  stall_o;
    output                  stall_o;
    input                   wb_clk;
    input                   wb_clk;
    input                   wb_rst;
    input                   wb_rst;
 
 
always @ (posedge wb_clk or posedge wb_rst)
always @ (posedge wb_clk or posedge wb_rst)
    if (wb_rst)
    if (wb_rst)
        wb_dat_o <= {dat_width{1'b0}};
        wb_dat_o <= {dat_width{1'b0}};
    else
    else
         case (wb_adr_i[adr_width-1:2])
         case (wb_adr_i[adr_width-1:2])
//E2_ifdef ROM
//E2_ifdef ROM
//E2_include `ROM
//E2_include `ROM
//E2_endif
//E2_endif
           default:
           default:
             wb_dat_o <= dat_default;
             wb_dat_o <= dat_default;
 
 
         endcase // case (wb_adr_i)
         endcase // case (wb_adr_i)
 
 
 
 
always @ (posedge wb_clk or posedge wb_rst)
always @ (posedge wb_clk or posedge wb_rst)
    if (wb_rst)
    if (wb_rst)
        wb_ack_o <= 1'b0;
        wb_ack_o <= 1'b0;
    else
    else
        wb_ack_o <= wb_stb_i & wb_cyc_i;
        wb_ack_o <= wb_stb_i & wb_cyc_i;
 
 
assign stall_o = 1'b0;
assign stall_o = 1'b0;
 
 
endmodule
endmodule
`endif
`endif
 
 
 
 
`ifdef WB_BOOT_ROM
`ifdef WB_BOOT_ROM
// WB ROM
// WB ROM
`define MODULE wb_boot_rom
`define MODULE wb_boot_rom
module `BASE`MODULE (
module `BASE`MODULE (
`undef MODULE
`undef MODULE
    wb_adr_i, wb_stb_i, wb_cyc_i,
    wb_adr_i, wb_stb_i, wb_cyc_i,
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
 
 
    parameter adr_hi = 31;
    parameter adr_hi = 31;
    parameter adr_lo = 28;
    parameter adr_lo = 28;
    parameter adr_sel = 4'hf;
    parameter adr_sel = 4'hf;
    parameter addr_width = 5;
    parameter addr_width = 5;
/*
/*
//E2_ifndef BOOT_ROM
//E2_ifndef BOOT_ROM
//E2_define BOOT_ROM "boot_rom.v"
//E2_define BOOT_ROM "boot_rom.v"
//E2_endif
//E2_endif
*/
*/
    input [adr_hi:2]    wb_adr_i;
    input [adr_hi:2]    wb_adr_i;
    input               wb_stb_i;
    input               wb_stb_i;
    input               wb_cyc_i;
    input               wb_cyc_i;
    output [31:0]        wb_dat_o;
    output [31:0]        wb_dat_o;
    output              wb_ack_o;
    output              wb_ack_o;
    output              hit_o;
    output              hit_o;
    input               wb_clk;
    input               wb_clk;
    input               wb_rst;
    input               wb_rst;
 
 
    wire hit;
    wire hit;
    reg [31:0] wb_dat;
    reg [31:0] wb_dat;
    reg wb_ack;
    reg wb_ack;
 
 
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
 
 
always @ (posedge wb_clk or posedge wb_rst)
always @ (posedge wb_clk or posedge wb_rst)
    if (wb_rst)
    if (wb_rst)
        wb_dat <= 32'h15000000;
        wb_dat <= 32'h15000000;
    else
    else
         case (wb_adr_i[addr_width-1:2])
         case (wb_adr_i[addr_width-1:2])
//E2_ifdef BOOT_ROM
//E2_ifdef BOOT_ROM
//E2_include `BOOT_ROM
//E2_include `BOOT_ROM
//E2_endif
//E2_endif
           /*
           /*
            // Zero r0 and jump to 0x00000100
            // Zero r0 and jump to 0x00000100
            0 : wb_dat <= 32'h18000000;
            0 : wb_dat <= 32'h18000000;
            1 : wb_dat <= 32'hA8200000;
            1 : wb_dat <= 32'hA8200000;
            2 : wb_dat <= 32'hA8C00100;
            2 : wb_dat <= 32'hA8C00100;
            3 : wb_dat <= 32'h44003000;
            3 : wb_dat <= 32'h44003000;
            4 : wb_dat <= 32'h15000000;
            4 : wb_dat <= 32'h15000000;
            */
            */
           default:
           default:
             wb_dat <= 32'h00000000;
             wb_dat <= 32'h00000000;
 
 
         endcase // case (wb_adr_i)
         endcase // case (wb_adr_i)
 
 
 
 
always @ (posedge wb_clk or posedge wb_rst)
always @ (posedge wb_clk or posedge wb_rst)
    if (wb_rst)
    if (wb_rst)
        wb_ack <= 1'b0;
        wb_ack <= 1'b0;
    else
    else
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
 
 
assign hit_o = hit;
assign hit_o = hit;
assign wb_dat_o = wb_dat & {32{wb_ack}};
assign wb_dat_o = wb_dat & {32{wb_ack}};
assign wb_ack_o = wb_ack;
assign wb_ack_o = wb_ack;
 
 
endmodule
endmodule
`endif
`endif
 
 
`ifdef WB_DPRAM
`ifdef WB_B3_DPRAM
`define MODULE wb_dpram
`define MODULE wb_b3_dpram
module `BASE`MODULE (
module `BASE`MODULE (
`undef MODULE
`undef MODULE
        // wishbone slave side a
        // wishbone slave side a
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
        wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
        wbsa_clk, wbsa_rst,
        wbsa_clk, wbsa_rst,
        // wishbone slave side a
        // wishbone slave side b
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
        wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
        wbsb_clk, wbsb_rst);
        wbsb_clk, wbsb_rst);
 
 
parameter data_width = 32;
parameter data_width_a = 32;
parameter addr_width = 8;
parameter data_width_b = data_width_a;
 
parameter addr_width_a = 8;
parameter dat_o_mask_a = 1;
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
parameter dat_o_mask_b = 1;
   parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
 
parameter max_burst_width_a = 4;
input [31:0] wbsa_dat_i;
parameter max_burst_width_b = max_burst_width_a;
input [addr_width-1:2] wbsa_adr_i;
 
 
input [data_width_a-1:0] wbsa_dat_i;
 
input [addr_width_a-1:0] wbsa_adr_i;
 
input [data_width_a/8-1:0] wbsa_sel_i;
 
input [2:0] wbsa_cti_i;
 
input [1:0] wbsa_bte_i;
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
output [31:0] wbsa_dat_o;
output [data_width_a-1:0] wbsa_dat_o;
output wbsa_ack_o;
output wbsa_ack_o;
input wbsa_clk, wbsa_rst;
input wbsa_clk, wbsa_rst;
 
 
input [31:0] wbsb_dat_i;
input [data_width_b-1:0] wbsb_dat_i;
input [addr_width-1:2] wbsb_adr_i;
input [addr_width_b-1:0] wbsb_adr_i;
 
input [data_width_b/8-1:0] wbsb_sel_i;
 
input [2:0] wbsb_cti_i;
 
input [1:0] wbsb_bte_i;
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
output [31:0] wbsb_dat_o;
output [data_width_b-1:0] wbsb_dat_o;
output wbsb_ack_o;
output wbsb_ack_o;
input wbsb_clk, wbsb_rst;
input wbsb_clk, wbsb_rst;
 
 
wire wbsa_dat_tmp, wbsb_dat_tmp;
wire [addr_width_a-1:0] adr_a;
 
wire [addr_width_b-1:0] adr_b;
 
 
`define MODULE dpram_2r2w
`define MODULE wb_adr_inc
`BASE`MODULE # (
`BASE`MODULE # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
 
    .cyc_i(wbsa_cyc_i),
 
    .stb_i(wbsa_stb_i),
 
    .cti_i(wbsa_cti_i),
 
    .bte_i(wbsa_bte_i),
 
    .adr_i(wbsa_adr_i),
 
    .we_i(wbsa_we_i),
 
    .ack_o(wbsa_ack_o),
 
    .adr_o(adr_a),
 
    .clk(wbsa_clk),
 
    .rst(wbsa_rst));
 
 
 
`BASE`MODULE # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
 
    .cyc_i(wbsb_cyc_i),
 
    .stb_i(wbsb_stb_i),
 
    .cti_i(wbsb_cti_i),
 
    .bte_i(wbsb_bte_i),
 
    .adr_i(wbsb_adr_i),
 
    .we_i(wbsb_we_i),
 
    .ack_o(wbsb_ack_o),
 
    .adr_o(adr_b),
 
    .clk(wbsb_clk),
 
    .rst(wbsb_rst));
 
`undef MODULE
 
 
 
`define MODULE dpram_be_2r2w
 
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size))
`undef MODULE
`undef MODULE
    .data_width(data_width), .addr_width(addr_width) )
ram_i (
dpram0(
 
    .d_a(wbsa_dat_i),
    .d_a(wbsa_dat_i),
    .q_a(wbsa_dat_tmp),
    .q_a(wbsa_dat_o),
    .adr_a(wbsa_adr_i),
    .adr_a(adr_a),
    .we_a(wbsa_we_i),
    .be_a(wbsa_sel_i),
 
    .we_a(wbsa_we_i & wbsa_ack_o),
    .clk_a(wbsa_clk),
    .clk_a(wbsa_clk),
    .d_b(wbsb_dat_i),
    .d_b(wbsb_dat_i),
    .q_b(wbsb_dat_tmp),
    .q_b(wbsb_dat_o),
    .adr_b(wbsb_adr_i),
    .adr_b(adr_b),
    .we_b(wbsb_we_i),
    .be_b(wbsb_sel_i),
 
    .we_b(wbsb_we_i & wbsb_ack_o),
    .clk_b(wbsb_clk) );
    .clk_b(wbsb_clk) );
 
 
generate if (dat_o_mask_a==1)
 
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
 
endgenerate
 
generate if (dat_o_mask_a==0)
 
    assign wbsa_dat_o = wbsa_dat_tmp;
 
endgenerate
 
 
 
generate if (dat_o_mask_b==1)
 
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
 
endgenerate
 
generate if (dat_o_mask_b==0)
 
    assign wbsb_dat_o = wbsb_dat_tmp;
 
endgenerate
 
 
 
`define MODULE spr
 
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
 
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
 
`undef MODULE
 
 
 
endmodule
endmodule
`endif
`endif
 
 

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