| Line 1149... |
Line 1149... |
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parameter dw_s = 32;
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parameter dw_s = 32;
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parameter aw_s = 24;
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parameter aw_s = 24;
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parameter dw_m = dw_s;
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parameter dw_m = dw_s;
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parameter aw_m = dw_s * aw_s / dw_m;
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parameter aw_m = dw_s * aw_s / dw_m;
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parameter max_burst_width = 4;
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parameter nr_of_ways = 1;
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parameter async = 1; // wbs_clk != wbm_clk
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parameter aw_cache_mem = 10;
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parameter nr_of_cache_lines = 1 << aw_tag_mem;
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parameter size_of_cache_lines = 4; // size in word with dw_s bits
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parameter nr_of_ways = 1;
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parameter aw_offset = 4; // 4 => 16 words per cache line
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parameter aw_slot = 10;
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localparam aw_tag = aw_s - aw_tag_mem - aw_offset;
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parameter wbm_burst_size = 4; // valid options 4,8,16
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`define SIZE2WIDTH wbm_burst_size
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localparam wbm_burst_width `SIZE2WIDTH_EXPR
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`undef SIZE2WIDTH
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localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
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`define SIZE2WIDTH nr_of_wbm_burst
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localparam nr_of_wbm_burst_width `SIZE2WIDTH_EXPR
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`undef SIZE2WIDTH
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input [dw_s-1:0] wbs_dat_i;
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input [dw_s-1:0] wbs_dat_i;
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input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
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input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
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input [dw_s/8-1:0] wbs-sel_i;
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input [dw_s/8-1:0] wbs-sel_i;
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input [2:0] wbs_cti_i;
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input [2:0] wbs_cti_i;
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input [1:0] wbs_bte_i;
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input [1:0] wbs_bte_i;
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| Line 1176... |
Line 1186... |
input wbm_ack_i;
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input wbm_ack_i;
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input wbm_stall_i;
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input wbm_stall_i;
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input wbm_clk, wbm_rst;
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input wbm_clk, wbm_rst;
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wire dirty, valid;
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wire dirty, valid;
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wire [] tag;
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wire [aw_tag-1:0] tag;
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wire tag_mem_we;
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wire [aw_tag-1:0] wbs_adr_tag;
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wire [aw_slot-1:0] wbs_adr_slot;
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wire [aw_offset_1:0] wbs_adr_word;
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wire [aw-1:0] wbs_adr;
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reg [1:0] state;
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localparam idle = 2'h0;
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localparam rdwr = 2'h1;
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localparam push = 2'h2;
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localparam pull = 2'h3;
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wire eoc;
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// cdc
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wire done, mem_alert, mem_done;
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assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
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assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
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`define MODULE ram
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`BASE`MODULE
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# ( .data_width(aw_tag), .addr_Width(aw_slot))
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tag_mem ( .d(wbs_adr_slot), .adr(wbs_adr_tag), .we(done), .q(tag), .clk(wbs_clk));
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`undef MODULE
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assign valid = wbs_adr_tag == tag;
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`define MODULE wb_adr_inc
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`define MODULE wb_adr_inc
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`BASE`MODULE # ( .adr_width(aw), .max_burst_width(max_burst_width)) adr_inc0 (
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`BASE`MODULE # ( .adr_width(aw_slot+aw_offset), .max_burst_width(max_burst_width)) adr_inc0 (
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.cyc_i(wbs_cyc_i),
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.cyc_i(wbs_cyc_i),
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.stb_i(wbs_stb_i),
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.stb_i(wbs_stb_i & (state==idle | (state==rw & valid))), // throttle depending on valid
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.cti_i(wbs_cti_i),
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.cti_i(wbs_cti_i),
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.bte_i(wbs_bte_i),
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.bte_i(wbs_bte_i),
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.adr_i(wbs_adr_i),
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.adr_i(wbs_adr_i),
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.we_i(wbs_we_i),
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.we_i(wbs_we_i),
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.ack_o(wbs_ack_o),
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.ack_o(wbs_ack_o),
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.adr_o(adr),
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.adr_o(wbs_adr),
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.clk(wb_clk),
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.clk(wbsa_clk),
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.rst(wb_rst));
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.rst(wbsa_rst));
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`undef MODULE
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`define MODULE dpram_be_2r2w
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`BASE`MODULE
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# ( .data_width(aw_tag), .addr_Width(aw_slot+aw_offset))
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cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr), be_a(wbs_sel_i), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .q_a(wbs_dat_o), .clk_a(wbs_clk),
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.d_b(wbm_dat_i), .adr_b(wbm_adr), be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
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`undef MODULE
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always @ (posedge wbs_clk or posedge wbs_rst)
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if (wbs_rst)
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case <= idle;
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else
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case (state)
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idle:
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if (wbs_cyc_i)
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state <= rdwr;
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rdwr:
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if (wbs_we_i & valid & eoc)
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state <= idle;
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else if (wbs_we_i & !valid)
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state <= pull;
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else if (!wbs_we_i & valid & eoc)
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state <= idle;
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else if (!wbs_we_i & !valid & !dirty)
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state <= pull;
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else if (!wbs_we_i & !valid & dirty)
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state <= push;
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push:
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if (done)
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state <= rdwr;
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pull:
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if (done)
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state <= rdwr;
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default: state <= idle;
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endcase
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// cdc
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generate
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if (async==1) begin : cdc0
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`define MODULE cdc
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`BASE`MODULE cdc0 ( .start_pl(state==rdwr & !valid), .take_it_pl(mem_alert), .take_it_grant_pl(mem_done), .got_it_pl(done), .clk_src(wbs_clk), .rst_src(wbs_rst), .clk_dst(wbm_clk), .rst_dst(wbm_rst));
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`undef MODULE
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`undef MODULE
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end
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else begin : nocdc
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assign mem_alert = state==rdwr & !valid;
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assign done = mem_done;
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end
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endgenerate
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always @ (posedge wbm_clk or posedge wbm_rst)
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if (rst)
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wbm_burst_adr <= {aw_wbm_burst{1'b0}};
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else
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if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i))
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wbm_burst_adr <= wbm_burst_adr + (aw_wbm_burst)'d1
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// FSM generating a number of burts 4 cycles
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// actual number depends on data width ratio
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// nr_of_wbm_burst
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reg [wbm_burst_width-1:0] cnt0;
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reg [nr_of_wbm_burst_width-1:0] cnt1;
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always @ (posedge wbm_clk or posedge wbm_rst)
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if (wbm_rst)
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{cnt1,cnt0} <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
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else
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if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
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{cnt1,cnt0} <= (nr_of_wbm_burst_width+wbm_burst_width)1'd1;
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endmodule
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endmodule
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`endif
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`endif
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