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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Diff between revs 96 and 97

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Rev 96 Rev 97
Line 1149... Line 1149...
 
 
parameter dw_s = 32;
parameter dw_s = 32;
parameter aw_s = 24;
parameter aw_s = 24;
parameter dw_m = dw_s;
parameter dw_m = dw_s;
parameter aw_m = dw_s * aw_s / dw_m;
parameter aw_m = dw_s * aw_s / dw_m;
 
parameter max_burst_width = 4;
 
 
parameter nr_of_ways = 1;
parameter async = 1; // wbs_clk != wbm_clk
parameter aw_cache_mem = 10;
 
parameter nr_of_cache_lines = 1 << aw_tag_mem;
 
parameter size_of_cache_lines = 4; // size in word with dw_s bits
 
 
 
 
parameter nr_of_ways = 1;
 
parameter aw_offset = 4; // 4 => 16 words per cache line
 
parameter aw_slot = 10;
 
localparam aw_tag = aw_s - aw_tag_mem - aw_offset;
 
parameter wbm_burst_size = 4; // valid options 4,8,16
 
`define SIZE2WIDTH wbm_burst_size
 
localparam wbm_burst_width `SIZE2WIDTH_EXPR
 
`undef SIZE2WIDTH
 
localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
 
`define SIZE2WIDTH nr_of_wbm_burst
 
localparam nr_of_wbm_burst_width `SIZE2WIDTH_EXPR
 
`undef SIZE2WIDTH
input [dw_s-1:0] wbs_dat_i;
input [dw_s-1:0] wbs_dat_i;
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
input [dw_s/8-1:0] wbs-sel_i;
input [dw_s/8-1:0] wbs-sel_i;
input [2:0] wbs_cti_i;
input [2:0] wbs_cti_i;
input [1:0] wbs_bte_i;
input [1:0] wbs_bte_i;
Line 1176... Line 1186...
input wbm_ack_i;
input wbm_ack_i;
input wbm_stall_i;
input wbm_stall_i;
input wbm_clk, wbm_rst;
input wbm_clk, wbm_rst;
 
 
wire dirty, valid;
wire dirty, valid;
wire [] tag;
wire [aw_tag-1:0] tag;
 
wire tag_mem_we;
 
wire [aw_tag-1:0] wbs_adr_tag;
 
wire [aw_slot-1:0] wbs_adr_slot;
 
wire [aw_offset_1:0] wbs_adr_word;
 
wire [aw-1:0] wbs_adr;
 
 
 
reg [1:0] state;
 
localparam idle = 2'h0;
 
localparam rdwr = 2'h1;
 
localparam push = 2'h2;
 
localparam pull = 2'h3;
 
wire eoc;
 
 
 
// cdc
 
wire done, mem_alert, mem_done;
 
 
 
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
 
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
 
 
 
`define MODULE ram
 
`BASE`MODULE
 
    # ( .data_width(aw_tag), .addr_Width(aw_slot))
 
    tag_mem ( .d(wbs_adr_slot), .adr(wbs_adr_tag), .we(done), .q(tag), .clk(wbs_clk));
 
`undef MODULE
 
assign valid = wbs_adr_tag == tag;
 
 
`define MODULE wb_adr_inc
`define MODULE wb_adr_inc
`BASE`MODULE # ( .adr_width(aw), .max_burst_width(max_burst_width)) adr_inc0 (
`BASE`MODULE # ( .adr_width(aw_slot+aw_offset), .max_burst_width(max_burst_width)) adr_inc0 (
    .cyc_i(wbs_cyc_i),
    .cyc_i(wbs_cyc_i),
    .stb_i(wbs_stb_i),
    .stb_i(wbs_stb_i & (state==idle | (state==rw & valid))), // throttle depending on valid
    .cti_i(wbs_cti_i),
    .cti_i(wbs_cti_i),
    .bte_i(wbs_bte_i),
    .bte_i(wbs_bte_i),
    .adr_i(wbs_adr_i),
    .adr_i(wbs_adr_i),
    .we_i(wbs_we_i),
    .we_i(wbs_we_i),
    .ack_o(wbs_ack_o),
    .ack_o(wbs_ack_o),
    .adr_o(adr),
    .adr_o(wbs_adr),
    .clk(wb_clk),
    .clk(wbsa_clk),
    .rst(wb_rst));
    .rst(wbsa_rst));
 
`undef MODULE
 
 
 
`define MODULE dpram_be_2r2w
 
`BASE`MODULE
 
    # ( .data_width(aw_tag), .addr_Width(aw_slot+aw_offset))
 
    cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr), be_a(wbs_sel_i), .we_a(wbs_cyc_i &  wbs_we_i & wbs_ack_o), .q_a(wbs_dat_o), .clk_a(wbs_clk),
 
                .d_b(wbm_dat_i), .adr_b(wbm_adr), be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
 
`undef MODULE
 
 
 
always @ (posedge wbs_clk or posedge wbs_rst)
 
if (wbs_rst)
 
    case <= idle;
 
else
 
    case (state)
 
    idle:
 
        if (wbs_cyc_i)
 
            state <= rdwr;
 
    rdwr:
 
        if (wbs_we_i & valid & eoc)
 
            state <= idle;
 
        else if (wbs_we_i & !valid)
 
            state <= pull;
 
        else if (!wbs_we_i & valid & eoc)
 
            state <= idle;
 
        else if (!wbs_we_i & !valid & !dirty)
 
            state <= pull;
 
        else if (!wbs_we_i & !valid & dirty)
 
            state <= push;
 
    push:
 
        if (done)
 
            state <= rdwr;
 
    pull:
 
        if (done)
 
            state <= rdwr;
 
    default: state <= idle;
 
    endcase
 
 
 
 
 
// cdc
 
generate
 
if (async==1) begin : cdc0
 
`define MODULE cdc
 
`BASE`MODULE cdc0 ( .start_pl(state==rdwr & !valid), .take_it_pl(mem_alert), .take_it_grant_pl(mem_done), .got_it_pl(done), .clk_src(wbs_clk), .rst_src(wbs_rst), .clk_dst(wbm_clk), .rst_dst(wbm_rst));
`undef MODULE
`undef MODULE
 
end
 
else begin : nocdc
 
    assign mem_alert = state==rdwr & !valid;
 
    assign done = mem_done;
 
end
 
endgenerate
 
 
 
always @ (posedge wbm_clk or posedge wbm_rst)
 
if (rst)
 
    wbm_burst_adr <= {aw_wbm_burst{1'b0}};
 
else
 
    if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i))
 
        wbm_burst_adr <= wbm_burst_adr + (aw_wbm_burst)'d1
 
 
 
// FSM generating a number of burts 4 cycles
 
// actual number depends on data width ratio
 
// nr_of_wbm_burst
 
reg [wbm_burst_width-1:0] cnt0;
 
reg [nr_of_wbm_burst_width-1:0] cnt1;
 
 
 
always @ (posedge wbm_clk or posedge wbm_rst)
 
if (wbm_rst)
 
    {cnt1,cnt0} <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
 
else
 
    if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
 
        {cnt1,cnt0} <= (nr_of_wbm_burst_width+wbm_burst_width)1'd1;
 
 
 
 
endmodule
endmodule
`endif
`endif
 
 
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