OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [sim/] [rtl_sim/] [run/] [Makefile] - Diff between revs 102 and 136

Only display areas with differences | Details | Blame | View Log

Rev 102 Rev 136
VERILOG_FILES = ./../../../rtl/verilog/versatile_library.v
VERILOG_FILES = ./../../../rtl/verilog/versatile_library.v
 
INC_DIR = ./../../../rtl/verilog
 
 
tb_wb_b3_ram_be:
tb_wb_b3_ram_be:
        vppreproc --noline --noblank +define+SYSTEMVERILOG +define+WB_B3_RAM_BE $(VERILOG_FILES) > wb_b3_ram_be.v
        vppreproc --noline --noblank +define+SYSTEMVERILOG +define+WB_B3_RAM_BE $(VERILOG_FILES) > wb_b3_ram_be.v
        vlog -reportprogress 300 -work work /home/michael/work/ocsvn/versatile_library/trunk/sim/rtl_sim/run/wb_b3_ram_be.v
        vlog -reportprogress 300 -work work /home/michael/work/ocsvn/versatile_library/trunk/sim/rtl_sim/run/wb_b3_ram_be.v
        vlog -reportprogress 300 -work work /home/michael/work/ocsvn/versatile_library/trunk/bench/wbm.v
        vlog -reportprogress 300 -work work /home/michael/work/ocsvn/versatile_library/trunk/bench/wbm.v
        vlog -reportprogress 300 -work work /home/michael/work/ocsvn/versatile_library/trunk/bench/tb_wb_b3_ram_be.v
        vlog -reportprogress 300 -work work /home/michael/work/ocsvn/versatile_library/trunk/bench/tb_wb_b3_ram_be.v
        vsim -do "run 10 us" -l log.txt -c work.vl_wb_b3_ram_be_tb
        vsim -do "run 10 us" -l log.txt -c work.vl_wb_b3_ram_be_tb
tb_wb_b3_dpram:
tb_wb_b3_dpram:
        vppreproc --noline --noblank +define+SYSTEMVERILOG +define+WB_B3_DPRAM $(VERILOG_FILES) > wb_b3_dpram.v
        vppreproc --noline --noblank +define+SYSTEMVERILOG +define+WB_B3_DPRAM $(VERILOG_FILES) > wb_b3_dpram.v
        vlog -reportprogress 300 -work work ./wb_b3_dpram.v
        vlog -reportprogress 300 -work work ./wb_b3_dpram.v
        vlog -reportprogress 300 -work work ./../../../bench/wbm.v
        vlog -reportprogress 300 -work work ./../../../bench/wbm.v
        vlog -reportprogress 300 -work work ./../../../bench/tb_wb_b3_dpram.v
        vlog -reportprogress 300 -work work ./../../../bench/tb_wb_b3_dpram.v
tb_wb_cache:
tb_wb_cache:
        vppreproc --noline --noblank +define+SYSTEMVERILOG +define+WB_CACHE +define+WB_RAM +define+RAM_BE $(VERILOG_FILES) > wb_cache.v
        vppreproc --noline --noblank +define+SYSTEMVERILOG +incdir+$(INC_DIR) +define+WB_AVALON_MEM_CACHE +define+WB_RAM +define+RAM_BE +define+WB_AVALON_MEM_CACHE $(VERILOG_FILES) > wb_cache.v
        vlog -reportprogress 300 -work work ./wb_cache.v
        vlog -reportprogress 300 -work work ./wb_cache.v
        vlog -reportprogress 300 -work work ./../../../bench/wbm.v
        vlog -reportprogress 300 -work work ./../../../bench/wbm.v
        vlog -reportprogress 300 -work work ./../../../bench/tb_wb_cache.v
        vlog -reportprogress 300 -work work ./../../../bench/tb_wb_cache.v
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.