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---- ----
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---- ----
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---- VHDL Wishbone TESTBENCH ----
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---- VHDL Wishbone TESTBENCH ----
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---- ----
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---- ----
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---- This file is part of the vhdl_wb_tb project ----
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---- This file is part of the vhdl_wb_tb project ----
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---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
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---- https://opencores.org/project/vhdl_wb_tb ----
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---- ----
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---- ----
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---- This file contains the top functional module of the design ----
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---- This file contains the stimulator module of the design. ----
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---- under test. The top functional module will be enclosed by ----
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---- Modify the stimulator to stimulate your DUT ----
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---- the top module for synthesis or the tb_top for simulation. ----
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---- The stimulator is controlled by the testcase (tc_xxxx files)----
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---- The top module can contain some synthesis specific code, ----
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---- via a wishbone bus. ----
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---- where the tb_top contains simulation specific code. ----
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---- ----
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---- ----
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---- To Do: ----
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---- To Do: ----
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---- - ----
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---- - ----
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---- ----
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---- ----
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---- Author(s): ----
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---- Author(s): ----
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---- - Sinx, email@opencores.org ----
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---- - Sinx, sinx@opencores.org ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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-- SVN information
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---- SVN information
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--
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----
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-- $URL: $
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---- $URL: $
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-- $Revision: $
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---- $Revision: $
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-- $Date: $
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---- $Date: $
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-- $Author: $
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---- $Author: $
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-- $Id: $
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---- $Id: $
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--
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
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---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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end process;
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end process;
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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signals_o <= s_register0(signals_o'left downto 0);
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signals_o <= s_register0(signals_o'left downto 0);
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--============================================================================
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--============================================================================
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end rtl; --stimulator
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end rtl; --stimulator
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--============================================================================
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-- end of file
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--============================================================================
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---- end of file ----
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No newline at end of file
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