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[/] [vhdl_wb_tb/] [trunk/] [bench/] [vhdl/] [stimulator.vhd] - Diff between revs 2 and 4

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----                                                              ---- 
----                                                              ---- 
----  VHDL Wishbone TESTBENCH                                     ---- 
----  VHDL Wishbone TESTBENCH                                     ---- 
----                                                              ---- 
----                                                              ---- 
----  This file is part of the vhdl_wb_tb project                 ---- 
----  This file is part of the vhdl_wb_tb project                 ---- 
----  http://www.opencores.org/cores/vhdl_wb_tb/                  ---- 
----  https://opencores.org/project/vhdl_wb_tb                    ---- 
----                                                              ---- 
----                                                              ---- 
----  This file contains the top functional module of the design  ----
----  This file contains the stimulator module of the design.     ----
----  under test. The top functional module will be enclosed by   ----
----  Modify the stimulator to stimulate your DUT                 ----
----  the top module for synthesis or the tb_top for simulation.  ---- 
----  The stimulator is controlled by the testcase (tc_xxxx files)----
----  The top module can contain some synthesis specific code,    ----
----  via a wishbone bus.                                         ---- 
----  where the tb_top contains simulation specific code.          ----
 
----                                                              ---- 
----                                                              ---- 
----  To Do:                                                      ---- 
----  To Do:                                                      ---- 
----   -                                                          ---- 
----   -                                                          ---- 
----                                                              ---- 
----                                                              ---- 
----  Author(s):                                                  ---- 
----  Author(s):                                                  ---- 
----      - Sinx, email@opencores.org               ---- 
----      - Sinx, sinx@opencores.org                              ---- 
----                                                              ---- 
----                                                              ---- 
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--    SVN information
----    SVN information
--
----
--      $URL:  $
----      $URL:  $
-- $Revision:  $
---- $Revision:  $
--     $Date:  $
----     $Date:  $
--   $Author:  $
----   $Author:  $
--       $Id:  $
----       $Id:  $
--
 
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----                                                              ---- 
----                                                              ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
----                                                              ---- 
----                                                              ---- 
---- This source file may be used and distributed without         ---- 
---- This source file may be used and distributed without         ---- 
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    end process;
    end process;
  ------------------------------------------------------------------------------
  ------------------------------------------------------------------------------
  signals_o <= s_register0(signals_o'left downto 0);
  signals_o <= s_register0(signals_o'left downto 0);
--============================================================================
--============================================================================
end rtl; --stimulator
end rtl; --stimulator
--============================================================================
 
-- end of file
 
--============================================================================
 
 
 
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