----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- VHDL Wishbone TESTBENCH ----
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---- VHDL Wishbone TESTBENCH ----
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---- ----
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---- ----
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---- This file is part of the vhdl_wb_tb project ----
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---- This file is part of the vhdl_wb_tb project ----
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---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
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---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
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---- ----
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---- ----
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---- This file contains the highest (top) module of the test ----
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---- This file contains constants for the test bench, such as ----
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---- bench. ----
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---- register definitions. ----
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---- It instantiates the design under test (DUT), instantiates ----
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---- the stimulator module for test vector generation, ----
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---- instantiates the verifier module for result comparison, ----
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---- instantiates the test case top (testcase_top) bfm, ----
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---- interconnects all three components, generates DUT-external ----
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---- clocks and resets. ----
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---- ----
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---- ----
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---- To Do: ----
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---- To Do: ----
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---- - ----
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---- - ----
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---- ----
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---- ----
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---- Author(s): ----
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---- Author(s): ----
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---- - Sinx, email@opencores.org ----
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---- - Sinx, sinx@opencores.org ----
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---- ----
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---- ----
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----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
-- SVN information
|
---- SVN information
|
--
|
----
|
-- $URL: $
|
---- $URL: $
|
-- $Revision: $
|
---- $Revision: $
|
-- $Date: $
|
---- $Date: $
|
-- $Author: $
|
---- $Author: $
|
-- $Id: $
|
---- $Id: $
|
--
|
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
---- ----
|
---- ----
|
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
|
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
|
---- ----
|
---- ----
|
---- This source file may be used and distributed without ----
|
---- This source file may be used and distributed without ----
|
---- restriction provided that this copyright statement is not ----
|
---- restriction provided that this copyright statement is not ----
|
---- removed from the file and that any derivative work contains ----
|
---- removed from the file and that any derivative work contains ----
|
---- the original copyright notice and the associated disclaimer. ----
|
---- the original copyright notice and the associated disclaimer. ----
|
---- ----
|
---- ----
|
---- This source file is free software; you can redistribute it ----
|
---- This source file is free software; you can redistribute it ----
|
---- and/or modify it under the terms of the GNU Lesser General ----
|
---- and/or modify it under the terms of the GNU Lesser General ----
|
---- Public License as published by the Free Software Foundation; ----
|
---- Public License as published by the Free Software Foundation; ----
|
---- either version 2.1 of the License, or (at your option) any ----
|
---- either version 2.1 of the License, or (at your option) any ----
|
---- later version. ----
|
---- later version. ----
|
---- ----
|
---- ----
|
---- This source is distributed in the hope that it will be ----
|
---- This source is distributed in the hope that it will be ----
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
---- details. ----
|
---- details. ----
|
---- ----
|
---- ----
|
---- You should have received a copy of the GNU Lesser General ----
|
---- You should have received a copy of the GNU Lesser General ----
|
---- Public License along with this source; if not, download it ----
|
---- Public License along with this source; if not, download it ----
|
---- from http://www.opencores.org/lgpl.shtml ----
|
---- from http://www.opencores.org/lgpl.shtml ----
|
---- ----
|
---- ----
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
|
|
-- library -----------------------------------------------------------
|
-- library -----------------------------------------------------------
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
library work;
|
library work;
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use work.convert_pkg.all;
|
use work.convert_pkg.all;
|
use work.wishbone_pkg.all;
|
use work.wishbone_pkg.all;
|
use work.wishbone_bfm_pkg.all;
|
use work.wishbone_bfm_pkg.all;
|
|
|
-- package -----------------------------------------------------------
|
-- package -----------------------------------------------------------
|
package tb_pkg is
|
package tb_pkg is
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
-- address definitions
|
-- address definitions
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
-- ??? model registers
|
-- ??? model registers
|
constant stimuator_base_c : integer := 16#00000000#;
|
constant stimuator_base_c : integer := 16#00000000#;
|
constant stimulator_register0_c : integer := stimuator_base_c + 16#0000_0000#;
|
constant stimulator_register0_c : integer := stimuator_base_c + 16#0000_0000#;
|
constant stimulator_register1_c : integer := stimuator_base_c + 16#0000_0004#;
|
constant stimulator_register1_c : integer := stimuator_base_c + 16#0000_0004#;
|
|
|
-- ??? model registers
|
-- ??? model registers
|
constant verifier_base_c : integer := 16#10000000#;
|
constant verifier_base_c : integer := 16#10000000#;
|
constant verifier_register0_c : integer := verifier_base_c + 16#0000_0000#;
|
constant verifier_register0_c : integer := verifier_base_c + 16#0000_0000#;
|
constant verifier_register1_c : integer := verifier_base_c + 16#0000_0004#;
|
constant verifier_register1_c : integer := verifier_base_c + 16#0000_0004#;
|
constant verifier_register2_c : integer := verifier_base_c + 16#0000_0008#;
|
constant verifier_register2_c : integer := verifier_base_c + 16#0000_0008#;
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
end package;
|
end package;
|
--============================================================================
|
|
-- end of file
|
|
--============================================================================
|
|
No newline at end of file
|
No newline at end of file
|
|
----------------------------------------------------------------------
|
|
---- end of file ----
|
|
----------------------------------------------------------------------
|
No newline at end of file
|
No newline at end of file
|
