| Line 26... |
Line 26... |
---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- SVN information
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---- SVN information
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----
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----
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---- $URL: file:///svn/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/tb_top.vhd $
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---- $URL: file:///svn/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/tb_top.vhd $
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---- $Revision: 14 $
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---- $Revision: 18 $
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---- $Date: 2018-07-22 16:27:41 +0200 (Sun, 22 Jul 2018) $
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---- $Date: 2018-08-01 11:56:15 +0200 (Wed, 01 Aug 2018) $
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---- $Author: sinx $
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---- $Author: sinx $
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---- $Id: tb_top.vhd 14 2018-07-22 14:27:41Z sinx $
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---- $Id: tb_top.vhd 18 2018-08-01 09:56:15Z sinx $
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
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---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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| Line 139... |
Line 139... |
wb_bfm_in_s.dat <= (others => 'U');
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wb_bfm_in_s.dat <= (others => 'U');
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wb_bfm_in_s.ack <= '1';
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wb_bfm_in_s.ack <= '1';
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wb_bfm_in_s.clk <= wb_clock_s;
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wb_bfm_in_s.clk <= wb_clock_s;
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wb_bfm_in_s.int <= '0';
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wb_bfm_in_s.int <= '0';
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wb_bfm_in_s.rst <= wb_reset_s;
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wb_bfm_in_s.rst <= wb_reset_s;
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wb_bfm_in_s.tgd <= (others => '0');
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wb_bfm_in_s.err <= '0';
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wb_bfm_in_s.rty <= '0';
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for I in number_of_wb_slaves_c-1 downto 0 loop
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for I in number_of_wb_slaves_c-1 downto 0 loop
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wb_slaves_in_s(I) <= work.wishbone_pkg.wb_master_out_idle_c; -- default values are init (idle) values
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wb_slaves_in_s(I) <= work.wishbone_pkg.wb_master_out_idle_c; -- default values are init (idle) values
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wb_slaves_in_s(I).clk <= wb_clock_s;
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wb_slaves_in_s(I).clk <= wb_clock_s;
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wb_slaves_in_s(I).rst <= wb_reset_s OR wb_bfm_out_s.rst;
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wb_slaves_in_s(I).rst <= wb_reset_s OR wb_bfm_out_s.rst;
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if ( wb_bfm_out_s.adr(31 downto 28) = to_std_logic_vector(I,4)) then -- decode the upper nibble for module decoding
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if ( wb_bfm_out_s.adr(31 downto 28) = to_std_logic_vector(I,4)) then -- decode the upper nibble for module decoding
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wb_bfm_in_s.dat <= wb_slaves_out_s(I).dat;
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wb_bfm_in_s.dat <= wb_slaves_out_s(I).dat;
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wb_bfm_in_s.ack <= wb_slaves_out_s(I).ack;
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wb_bfm_in_s.ack <= wb_slaves_out_s(I).ack;
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wb_bfm_in_s.tgd <= wb_slaves_out_s(I).tgd;
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wb_bfm_in_s.err <= wb_slaves_out_s(I).err;
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wb_bfm_in_s.rty <= wb_slaves_out_s(I).rty;
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wb_slaves_in_s(I).dat <= wb_bfm_out_s.dat;
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wb_slaves_in_s(I).dat <= wb_bfm_out_s.dat;
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wb_slaves_in_s(I).tgd <= wb_bfm_out_s.tgd;
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wb_slaves_in_s(I).tgd <= wb_bfm_out_s.tgd;
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wb_slaves_in_s(I).adr <= wb_bfm_out_s.adr;
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wb_slaves_in_s(I).adr <= wb_bfm_out_s.adr;
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wb_slaves_in_s(I).cyc <= wb_bfm_out_s.cyc;
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wb_slaves_in_s(I).cyc <= wb_bfm_out_s.cyc;
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wb_slaves_in_s(I).lock <= wb_bfm_out_s.lock;
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wb_slaves_in_s(I).lock <= wb_bfm_out_s.lock;
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