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[/] [vhdl_wb_tb/] [trunk/] [bench/] [vhdl/] [tb_top.vhd] - Diff between revs 14 and 18

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Rev 14 Rev 18
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----                                                              ---- 
----                                                              ---- 
----------------------------------------------------------------------
----------------------------------------------------------------------
----    SVN information
----    SVN information
----
----
----      $URL: file:///svn/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/tb_top.vhd $
----      $URL: file:///svn/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/tb_top.vhd $
---- $Revision: 14 $
---- $Revision: 18 $
----     $Date: 2018-07-22 16:27:41 +0200 (Sun, 22 Jul 2018) $
----     $Date: 2018-08-01 11:56:15 +0200 (Wed, 01 Aug 2018) $
----   $Author: sinx $
----   $Author: sinx $
----       $Id: tb_top.vhd 14 2018-07-22 14:27:41Z sinx $
----       $Id: tb_top.vhd 18 2018-08-01 09:56:15Z sinx $
---------------------------------------------------------------------- 
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----                                                              ---- 
----                                                              ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
----                                                              ---- 
----                                                              ---- 
---- This source file may be used and distributed without         ---- 
---- This source file may be used and distributed without         ---- 
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      wb_bfm_in_s.dat <= (others => 'U');
      wb_bfm_in_s.dat <= (others => 'U');
      wb_bfm_in_s.ack <= '1';
      wb_bfm_in_s.ack <= '1';
      wb_bfm_in_s.clk <= wb_clock_s;
      wb_bfm_in_s.clk <= wb_clock_s;
      wb_bfm_in_s.int <= '0';
      wb_bfm_in_s.int <= '0';
      wb_bfm_in_s.rst <= wb_reset_s;
      wb_bfm_in_s.rst <= wb_reset_s;
 
      wb_bfm_in_s.tgd <= (others => '0');
 
      wb_bfm_in_s.err <= '0';
 
      wb_bfm_in_s.rty <= '0';
      for I in number_of_wb_slaves_c-1 downto 0 loop
      for I in number_of_wb_slaves_c-1 downto 0 loop
        wb_slaves_in_s(I) <= work.wishbone_pkg.wb_master_out_idle_c; -- default values are init (idle) values
        wb_slaves_in_s(I) <= work.wishbone_pkg.wb_master_out_idle_c; -- default values are init (idle) values
        wb_slaves_in_s(I).clk <= wb_clock_s;
        wb_slaves_in_s(I).clk <= wb_clock_s;
        wb_slaves_in_s(I).rst <= wb_reset_s OR wb_bfm_out_s.rst;
        wb_slaves_in_s(I).rst <= wb_reset_s OR wb_bfm_out_s.rst;
        if ( wb_bfm_out_s.adr(31 downto 28) = to_std_logic_vector(I,4)) then -- decode the upper nibble for module decoding
        if ( wb_bfm_out_s.adr(31 downto 28) = to_std_logic_vector(I,4)) then -- decode the upper nibble for module decoding
          wb_bfm_in_s.dat <= wb_slaves_out_s(I).dat;
          wb_bfm_in_s.dat <= wb_slaves_out_s(I).dat;
          wb_bfm_in_s.ack <= wb_slaves_out_s(I).ack;
          wb_bfm_in_s.ack <= wb_slaves_out_s(I).ack;
 
          wb_bfm_in_s.tgd <= wb_slaves_out_s(I).tgd;
 
          wb_bfm_in_s.err <= wb_slaves_out_s(I).err;
 
          wb_bfm_in_s.rty <= wb_slaves_out_s(I).rty;
          wb_slaves_in_s(I).dat <= wb_bfm_out_s.dat;
          wb_slaves_in_s(I).dat <= wb_bfm_out_s.dat;
          wb_slaves_in_s(I).tgd  <= wb_bfm_out_s.tgd;
          wb_slaves_in_s(I).tgd  <= wb_bfm_out_s.tgd;
          wb_slaves_in_s(I).adr  <= wb_bfm_out_s.adr;
          wb_slaves_in_s(I).adr  <= wb_bfm_out_s.adr;
          wb_slaves_in_s(I).cyc  <= wb_bfm_out_s.cyc;
          wb_slaves_in_s(I).cyc  <= wb_bfm_out_s.cyc;
          wb_slaves_in_s(I).lock <= wb_bfm_out_s.lock;
          wb_slaves_in_s(I).lock <= wb_bfm_out_s.lock;

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