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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- VHDL Wishbone TESTBENCH ----
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---- VHDL Wishbone TESTBENCH ----
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---- ----
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---- ----
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---- This file is part of the vhdl_wb_tb project ----
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---- This file is part of the vhdl_wb_tb project ----
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---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
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---- https://opencores.org/project/vhdl_wb_tb ----
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---- ----
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---- This file contains the highest (top) module for simulation. ----
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---- Like tb_top it instantiates the core_top module and ----
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---- provides parameters/generics. Where the top module provides ----
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---- parameters for synthesis this file provides parameters for ----
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---- simulation. ----
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---- ----
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---- ----
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---- This file contains the highest (top) module of the test ----
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---- bench. ----
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---- It instantiates the design under test (DUT), instantiates ----
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---- It instantiates the design under test (DUT), instantiates ----
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---- the stimulator module for test vector generation, ----
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---- the stimulator module for test vector generation, ----
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---- instantiates the verifier module for result comparison, ----
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---- instantiates the verifier module for result comparison, ----
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---- instantiates the test case top (testcase_top) bfm, ----
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---- instantiates the test case top (testcase_top) bfm, ----
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---- interconnects all three components, generates DUT-external ----
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---- interconnects all three components, generates DUT-external ----
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---- ----
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---- ----
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---- To Do: ----
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---- To Do: ----
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---- - ----
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---- - ----
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---- ----
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---- ----
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---- Author(s): ----
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---- Author(s): ----
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---- - Sinx, email@opencores.org ----
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---- - Sinx, sinx@opencores.org ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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-- SVN information
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---- SVN information
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--
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----
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-- $URL: $
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---- $URL: $
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-- $Revision: $
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---- $Revision: $
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-- $Date: $
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---- $Date: $
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-- $Author: $
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---- $Author: $
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-- $Id: $
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---- $Id: $
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--
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
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---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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entity tb_top is
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entity tb_top is
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-- empty entity, since this is the simulation top and all test cases are defined
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-- empty entity, since this is the simulation top and all test cases are defined
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-- in the tc_xxx files.
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-- in the tc_xxx files.
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end entity tb_top;
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end entity tb_top;
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--=architecture===============================================================
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-- architecture ------------------------------------------------------
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architecture rtl of tb_top is
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architecture rtl of tb_top is
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--============================================================================
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-----------------------------------------------------------------------------
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constant g_wb_clock_period : time := 20.0 ns; -- 50 mhz
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constant g_wb_clock_period : time := 20.0 ns; -- 50 mhz
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--============================================================================
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-- signal declaration
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--============================================================================
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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signal s_wb_bfm_out : wishbone_bfm_master_out_t; -- from testcase_top
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signal s_wb_bfm_out : wishbone_bfm_master_out_t; -- from testcase_top
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signal s_wb_bfm_in : wishbone_bfm_master_in_t; -- to testcase_top
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signal s_wb_bfm_in : wishbone_bfm_master_in_t; -- to testcase_top
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signal s_wb_master_out : wishbone_master_out_t; -- from wb_decoder
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signal s_wb_master_out : wishbone_master_out_t; -- from wb_decoder
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constant number_of_stimulus_signals_c : integer := 8;
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constant number_of_stimulus_signals_c : integer := 8;
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constant number_of_verify_signals_c : integer := 8;
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constant number_of_verify_signals_c : integer := 8;
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signal s_stimulus : std_logic_vector(number_of_stimulus_signals_c-1 downto 0);
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signal s_stimulus : std_logic_vector(number_of_stimulus_signals_c-1 downto 0);
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signal s_verify : std_logic_vector(number_of_verify_signals_c-1 downto 0);
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signal s_verify : std_logic_vector(number_of_verify_signals_c-1 downto 0);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- other signals
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-----------------------------------------------------------------------------
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begin
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begin
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--============================================================================
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-----------------------------------------------------------------------------
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--clocks---------------------------------------------------------------------
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--clocks---------------------------------------------------------------------
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wb_clock_generator : process -- required for test bench wb bus; 50mhz is standard
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wb_clock_generator : process -- required for test bench wb bus; 50mhz is standard
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begin
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begin
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s_wb_clock <= '0';
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s_wb_clock <= '0';
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wait for g_wb_clock_period/2;
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wait for g_wb_clock_period/2;
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end if;
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end if;
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end process;
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end process;
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s_wb_reset <= s_wb_reset_p2;
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s_wb_reset <= s_wb_reset_p2;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- instance of test case "player"; runs tc_xxxx modules
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-- instance of test case "player"; runs tc_xxxx modules
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testcase_top_inst : entity work.testcase_top
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tc_top_inst : entity work.tc_top
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port map (
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port map (
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wb_o => s_wb_bfm_out,
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wb_o => s_wb_bfm_out,
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wb_i => s_wb_bfm_in
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wb_i => s_wb_bfm_in
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);
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);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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wb_o => s_wb_slaves_out(1),
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wb_o => s_wb_slaves_out(1),
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signals_i => s_verify
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signals_i => s_verify
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);
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);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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end rtl;
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end rtl;
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--============================================================================
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-- end of file
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--============================================================================
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No newline at end of file
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----------------------------------------------------------------------
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---- end of file ----
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----------------------------------------------------------------------
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No newline at end of file
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