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[/] [vhdl_wb_tb/] [trunk/] [bench/] [vhdl/] [tc_xxxx.vhd] - Diff between revs 2 and 4

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----  VHDL Wishbone TESTBENCH                                     ---- 
----  VHDL Wishbone TESTBENCH                                     ---- 
----                                                              ---- 
----                                                              ---- 
----  This file is part of the vhdl_wb_tb project                 ---- 
----  This file is part of the vhdl_wb_tb project                 ---- 
----  http://www.opencores.org/cores/vhdl_wb_tb/                  ---- 
----  http://www.opencores.org/cores/vhdl_wb_tb/                  ---- 
----                                                              ---- 
----                                                              ---- 
----  This file contains the highest (top) module of the test     ----
----  This file contains the one test sequence for the test bench.----
----  bench.                                                      ---- 
----  Several test sequences shall be stored in several tc_xxxx   ---- 
----  It instantiates the design under test (DUT), instantiates   ----
----  files. This file contains the architecture for the tc_top   ----
----  the stimulator module for test vector generation,           ----
----  enity, lcated in tc_top.vhd.                                ----
----  instantiates the verifier module for result comparison,     ----
 
----  instantiates the test case top (testcase_top) bfm,          ----
 
----  interconnects all three components, generates DUT-external  ----
 
----  clocks and resets.                                          ----
 
----                                                              ---- 
----                                                              ---- 
----  To Do:                                                      ---- 
----  To Do:                                                      ---- 
----   -                                                          ---- 
----   -                                                          ---- 
----                                                              ---- 
----                                                              ---- 
----  Author(s):                                                  ---- 
----  Author(s):                                                  ---- 
----      - Sinx, email@opencores.org                             ---- 
----      - Sinx, sinx@opencores.org                              ---- 
----                                                              ---- 
----                                                              ---- 
----------------------------------------------------------------------
----------------------------------------------------------------------
--    SVN information
----    SVN information
--
----
--      $URL:  $
----      $URL:  $
-- $Revision:  $
---- $Revision:  $
--     $Date:  $
----     $Date:  $
--   $Author:  $
----   $Author:  $
--       $Id:  $
----       $Id:  $
--
 
---------------------------------------------------------------------- 
---------------------------------------------------------------------- 
----                                                              ---- 
----                                                              ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
----                                                              ---- 
----                                                              ---- 
---- This source file may be used and distributed without         ---- 
---- This source file may be used and distributed without         ---- 
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use work.wishbone_bfm_pkg.all;
use work.wishbone_bfm_pkg.all;
use work.my_project_pkg.all;
use work.my_project_pkg.all;
use work.tb_pkg.all;
use work.tb_pkg.all;
 
 
-- architecture ------------------------------------------------------
-- architecture ------------------------------------------------------
architecture tc_xxxx of testcase_top is
architecture tc_xxxx of tc_top is
  --==========================================================================
  ----------------------------------------------------------------------
  --  local constant definitions
  --  local constant definitions
  --==========================================================================
----------------------------------------------------------------------
  --==========================================================================
 
begin
begin
  --==========================================================================
  ----------------------------------------------------------------------
  tc_xxxx_proc : process
  tc_xxxx_proc : process
  begin
  begin
  --==========================================================================
  ----------------------------------------------------------------------
    -- standard signal initialization
    -- standard signal initialization
    wb_o <= wb_bfm_master_out_idle_c;
    wb_o <= wb_bfm_master_out_idle_c;
 
 
    wait until wb_i.rst = '0';
    wait until wb_i.rst = '0';
    wait until rising_edge(wb_i.clk);
    wait until rising_edge(wb_i.clk);
    wait until rising_edge(wb_i.clk);
    wait until rising_edge(wb_i.clk);
    --
    --
    wait for 400 ns;
    wait for 400 ns;
    wait until rising_edge(wb_i.clk);
    wait until rising_edge(wb_i.clk);
    --
    --
  --==========================================================================
  ----------------------------------------------------------------------
 
 
    report "-----------------------------------------------------------------";
    report "-----------------------------------------------------------------";
    report "-- tc_xxxx: ADD_DESCRIPTION_HERE                               --";
    report "-- tc_xxxx: ADD_DESCRIPTION_HERE                               --";
    report "-----------------------------------------------------------------";
    report "-----------------------------------------------------------------";
    --
    --
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    report "-----------------------------------------------------------------";
    report "-----------------------------------------------------------------";
    wait for 6 us;
    wait for 6 us;
    wait until rising_edge(wb_i.clk);
    wait until rising_edge(wb_i.clk);
    wb_read (verifier_register2_c, 16#0000_0005#, wb_i, wb_o);
    wb_read (verifier_register2_c, 16#0000_0005#, wb_i, wb_o);
    wait for 1 us;
    wait for 1 us;
    -- =================================================
  ----------------------------------------------------------------------
    report "-- tc_xxxx finished";
    report "-- tc_xxxx finished";
    -- =================================================
  ----------------------------------------------------------------------
    --
 
    wait for 400 ns;
 
    --wait;
 
    --
    --
    report "test case tc_xxxx completed successfully"; --severity failure;
    report "test case tc_xxxx completed successfully"; --severity failure;
    report "-----------------------------------------------------------------";
    report "-----------------------------------------------------------------";
    report "-----------------------------------------------------------------";
    report "-----------------------------------------------------------------";
    std.env.stop; -- pause simulation
    wait for 100 ns;
 
 
    --std.env.finish; -- stop simulation; end modelsim
    if (exit_simulator_at_tc_end_c/="1") then
 
      std.env.stop; -- pause simulation
 
    else
 
      std.env.finish; -- stop simulation
 
    end if;
  end process tc_xxxx_proc;
  end process tc_xxxx_proc;
  --==========================================================================
  ----------------------------------------------------------------------
end tc_xxxx;
end tc_xxxx;
--============================================================================
 
-- end of file
 
--============================================================================
 
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----------------------------------------------------------------------
 
---- end of file                                                  ---- 
 
----------------------------------------------------------------------
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