| Line 3... |
Line 3... |
---- VHDL Wishbone TESTBENCH ----
|
---- VHDL Wishbone TESTBENCH ----
|
---- ----
|
---- ----
|
---- This file is part of the vhdl_wb_tb project ----
|
---- This file is part of the vhdl_wb_tb project ----
|
---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
|
---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
|
---- ----
|
---- ----
|
---- This file contains the top functional module of the design ----
|
---- This file contains the verifier module which monitors the ----
|
---- under test. The top functional module will be enclosed by ----
|
---- DUTs responses. It is controlled via a wishbone interface ----
|
---- the top module for synthesis or the tb_top for simulation. ----
|
---- by the tc_xxxx files. ----
|
---- The top module can contain some synthesis specific code, ----
|
---- It can check the signals by itself or forward information ----
|
---- where the tb_top contains simulation specific code. ----
|
---- To the tc_xxxx files. ----
|
---- ----
|
---- ----
|
---- To Do: ----
|
---- To Do: ----
|
---- - ----
|
---- - ----
|
---- ----
|
---- ----
|
---- Author(s): ----
|
---- Author(s): ----
|
---- - Sinx, email@opencores.org ----
|
---- - Sinx, sinx@opencores.org ----
|
---- ----
|
---- ----
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
-- SVN information
|
---- SVN information
|
--
|
----
|
-- $URL: $
|
---- $URL: $
|
-- $Revision: $
|
---- $Revision: $
|
-- $Date: $
|
---- $Date: $
|
-- $Author: $
|
---- $Author: $
|
-- $Id: $
|
---- $Id: $
|
--
|
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
---- ----
|
---- ----
|
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
|
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
|
---- ----
|
---- ----
|
---- This source file may be used and distributed without ----
|
---- This source file may be used and distributed without ----
|
| Line 74... |
Line 73... |
|
|
signals_i : in std_logic_vector(g_number_of_signals-1 downto 0)
|
signals_i : in std_logic_vector(g_number_of_signals-1 downto 0)
|
);
|
);
|
end verifier;
|
end verifier;
|
|
|
--=architecture===============================================================
|
-- architecture ----------------------------------------------------------------
|
architecture rtl of verifier is
|
architecture rtl of verifier is
|
--============================================================================
|
------------------------------------------------------------------------------
|
-- signal declaration
|
-- signal declaration
|
--============================================================================
|
------------------------------------------------------------------------------
|
signal s_register0 : std_logic_vector(31 downto 0);
|
signal s_register0 : std_logic_vector(31 downto 0);
|
signal s_register1 : std_logic_vector(31 downto 0);
|
signal s_register1 : std_logic_vector(31 downto 0);
|
--============================================================================
|
------------------------------------------------------------------------------
|
begin
|
begin
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
wb_o.ack <= '1';
|
wb_o.ack <= '1';
|
wb_o.err <= '0';
|
wb_o.err <= '0';
|
wb_o.rty <= '0';
|
wb_o.rty <= '0';
|
| Line 125... |
Line 124... |
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
--============================================================================
|
|
end rtl; --verifier
|
end rtl; --verifier
|
--============================================================================
|
|
-- end of file
|
|
--============================================================================
|
|
|
|
No newline at end of file
|
No newline at end of file
|
|
----------------------------------------------------------------------
|
|
---- end of file ----
|
|
----------------------------------------------------------------------
|
No newline at end of file
|
No newline at end of file
|
