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[/] [vhdl_wb_tb/] [trunk/] [bench/] [vhdl/] [wishbone_bfm_pkg.vhd] - Diff between revs 23 and 27

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Rev 23 Rev 27
Line 16... Line 16...
----                                                              ---- 
----                                                              ---- 
---------------------------------------------------------------------- 
---------------------------------------------------------------------- 
----    SVN information
----    SVN information
----
----
----      $URL: file:///svn/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/wishbone_bfm_pkg.vhd $
----      $URL: file:///svn/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/wishbone_bfm_pkg.vhd $
---- $Revision: 23 $
---- $Revision: 27 $
----     $Date: 2018-08-01 12:40:03 +0200 (Wed, 01 Aug 2018) $
----     $Date: 2019-09-21 17:20:11 +0200 (Sat, 21 Sep 2019) $
----   $Author: sinx $
----   $Author: sinx $
----       $Id: wishbone_bfm_pkg.vhd 23 2018-08-01 10:40:03Z sinx $
----       $Id: wishbone_bfm_pkg.vhd 27 2019-09-21 15:20:11Z sinx $
---------------------------------------------------------------------- 
---------------------------------------------------------------------- 
----                                                              ---- 
----                                                              ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
----                                                              ---- 
----                                                              ---- 
---- This source file may be used and distributed without         ---- 
---- This source file may be used and distributed without         ---- 
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    end loop;
    end loop;
    o           <= wb_bfm_master_out_idle_c; -- reset bus
    o           <= wb_bfm_master_out_idle_c; -- reset bus
 
 
    if (verbose_mode_i = 2) then  -- output all
    if (verbose_mode_i = 2) then  -- output all
      report message_prolog_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
      report message_prolog_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
        " was: 0x" & to_string(readdata_v, 16, wishbone_data_width_c/4)
        " was: 0x" & to_string(read_data_o, 16, wishbone_data_width_c/4)
        severity note;
        severity note;
 
     end if;
  end wb_read;
  end wb_read;
  ------------------------------------------------------------------------
  ------------------------------------------------------------------------
  ------------------------------------------------------------------------
  ------------------------------------------------------------------------
  procedure wb_read(
  procedure wb_read(
    address_i                   : in  integer; -- address to read from
    address_i                   : in  integer; -- address to read from

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