| Line 10... |
Line 10... |
---- ----
|
---- ----
|
---- To Do: ----
|
---- To Do: ----
|
---- - ----
|
---- - ----
|
---- ----
|
---- ----
|
---- Author(s): ----
|
---- Author(s): ----
|
---- - Sinx, email@opencores.org ----
|
---- - Sinx, sinx@opencores.org ----
|
---- ----
|
---- ----
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
-- SVN information
|
---- SVN information
|
--
|
----
|
-- $URL: $
|
---- $URL: $
|
-- $Revision: $
|
---- $Revision: $
|
-- $Date: $
|
---- $Date: $
|
-- $Author: $
|
---- $Author: $
|
-- $Id: $
|
---- $Id: $
|
--
|
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
---- ----
|
---- ----
|
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
|
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
|
---- ----
|
---- ----
|
---- This source file may be used and distributed without ----
|
---- This source file may be used and distributed without ----
|
| Line 106... |
Line 105... |
stb => '0',
|
stb => '0',
|
tga => (others=>'0'),
|
tga => (others=>'0'),
|
tgc => (others=>'0'),
|
tgc => (others=>'0'),
|
we => '0'
|
we => '0'
|
);
|
);
|
----------------------------------------------------------------------
|
|
-- BUS FUNCTIONS -----------------------------------------------------
|
-- BUS FUNCTIONS -----------------------------------------------------
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
|
----------------------------------------------------------------------
|
-- generate single write cycle
|
-- generate single write cycle
|
PROCEDURE wb_write(
|
procedure wb_write(
|
address_i : IN integer; -- address to write to
|
address_i : in integer; -- address to write to
|
data_i : IN integer; -- data value to be written
|
data_i : in integer; -- data value to be written
|
SIGNAL i : IN wishbone_bfm_master_in_t; -- incoming wb signals
|
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals
|
SIGNAL o : OUT wishbone_bfm_master_out_t; -- incoming wb signals
|
signal o : out wishbone_bfm_master_out_t; -- incoming wb signals
|
display_error_message_i : IN integer range 0 to 2 := 1; -- verbose mode; 0=no output, 1=error only, 2= all
|
display_error_message_i : in integer range 0 to 2 := 1; -- verbose mode; 0=no output, 1=error only, 2= all
|
additional_error_message_i : IN string := ""
|
additional_error_message_i : in string := ""
|
);
|
);
|
|
|
-- generate single read cycle and verify read word with expected_data_i
|
-- generate single read cycle and verify read word with expected_data_i
|
PROCEDURE wb_read(
|
procedure wb_read(
|
address_i : IN INTEGER;
|
address_i : in integer;
|
expected_data_i : IN INTEGER;
|
expected_data_i : in integer;
|
SIGNAL i : IN wishbone_bfm_master_in_t;
|
signal i : in wishbone_bfm_master_in_t;
|
SIGNAL o : OUT wishbone_bfm_master_out_t;
|
signal o : out wishbone_bfm_master_out_t;
|
display_error_message_i : IN integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp.
|
display_error_message_i : in integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp.
|
additional_error_message_i : IN STRING := "";
|
additional_error_message_i : in string := "";
|
expected_data_mask_i : IN INTEGER := 0
|
expected_data_mask_i : in integer := 0
|
);
|
);
|
|
|
-- generate single read cycle and return read data via read_data_o
|
-- generate single read cycle and return read data via read_data_o
|
PROCEDURE wb_read(
|
procedure wb_read(
|
address_i : IN INTEGER;
|
address_i : in integer;
|
read_data_o : OUT STD_LOGIC_VECTOR (wishbone_address_width_c-1 DOWNTO 0);
|
read_data_o : out std_logic_vector (wishbone_address_width_c-1 downto 0);
|
SIGNAL i : IN wishbone_bfm_master_in_t;
|
signal i : in wishbone_bfm_master_in_t;
|
SIGNAL o : OUT wishbone_bfm_master_out_t
|
signal o : out wishbone_bfm_master_out_t
|
);
|
);
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
end;
|
end;
|
|
|
-- package body ------------------------------------------------------
|
-- package body ------------------------------------------------------
|
package body wishbone_bfm_pkg is
|
package body wishbone_bfm_pkg is
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
PROCEDURE wb_write(
|
procedure wb_write(
|
address_i : IN integer;
|
address_i : in integer;
|
data_i : IN integer;
|
data_i : in integer;
|
SIGNAL i : IN wishbone_bfm_master_in_t;
|
signal i : in wishbone_bfm_master_in_t;
|
SIGNAL o : OUT wishbone_bfm_master_out_t;
|
signal o : out wishbone_bfm_master_out_t;
|
display_error_message_i : IN integer range 0 to 2 := 1;
|
display_error_message_i : in integer range 0 to 2 := 1;
|
additional_error_message_i : IN string := ""
|
additional_error_message_i : in string := ""
|
) IS
|
) is
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
BEGIN
|
begin
|
o.adr <= to_std_logic_vector(address_i, wishbone_address_width_c);
|
o.adr <= to_std_logic_vector(address_i, wishbone_address_width_c);
|
o.dat <= to_std_logic_vector(data_i, wishbone_address_width_c);
|
o.dat <= to_std_logic_vector(data_i, wishbone_address_width_c);
|
o.we <= '1';
|
o.we <= '1';
|
o.rst <= '0';
|
o.rst <= '0';
|
o.tgd <= (others => '0');
|
o.tgd <= (others => '0');
|
| Line 165... |
Line 164... |
o.lock <= '1';
|
o.lock <= '1';
|
o.sel <= (others => '1');
|
o.sel <= (others => '1');
|
o.stb <= '1';
|
o.stb <= '1';
|
o.tga <= (others => '0');
|
o.tga <= (others => '0');
|
o.tgc <= (others => '0');
|
o.tgc <= (others => '0');
|
IF (display_error_message_i = 2) THEN
|
if (display_error_message_i = 2) then
|
REPORT "Writing :" & to_string(data_i, 16, wishbone_address_width_c/4) & " to: " & to_string(address_i, 16, wishbone_address_width_c/4) &
|
report "writing :" & to_string(data_i, 16, wishbone_address_width_c/4) & " to: " & to_string(address_i, 16, wishbone_address_width_c/4) &
|
additional_error_message_i;
|
additional_error_message_i;
|
END IF;
|
end if;
|
|
|
WAIT UNTIL falling_edge(i.clk);
|
wait until falling_edge(i.clk);
|
-- wait for ack
|
-- wait for ack
|
WHILE i.ack = '0' LOOP
|
while i.ack = '0' loop
|
WAIT UNTIL falling_edge(i.clk);
|
wait until falling_edge(i.clk);
|
END LOOP;
|
end loop;
|
WAIT UNTIL rising_edge(i.clk);
|
wait until rising_edge(i.clk);
|
o <= wb_bfm_master_out_idle_c; -- reset bus
|
o <= wb_bfm_master_out_idle_c; -- reset bus
|
END wb_write;
|
end wb_write;
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
PROCEDURE wb_read(
|
procedure wb_read(
|
address_i : IN INTEGER;
|
address_i : in integer;
|
read_data_o : OUT STD_LOGIC_VECTOR (wishbone_address_width_c-1 DOWNTO 0);
|
read_data_o : out std_logic_vector (wishbone_address_width_c-1 downto 0);
|
SIGNAL i : IN wishbone_bfm_master_in_t;
|
signal i : in wishbone_bfm_master_in_t;
|
SIGNAL o : OUT wishbone_bfm_master_out_t
|
signal o : out wishbone_bfm_master_out_t
|
) IS
|
) is
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
BEGIN
|
begin
|
o.adr <= to_std_logic_vector(address_i, wishbone_address_width_c);
|
o.adr <= to_std_logic_vector(address_i, wishbone_address_width_c);
|
o.dat <= (others => 'U');
|
o.dat <= (others => 'U');
|
o.we <= '0';
|
o.we <= '0';
|
o.rst <= '0';
|
o.rst <= '0';
|
o.tgd <= (others => '0');
|
o.tgd <= (others => '0');
|
| Line 199... |
Line 198... |
o.lock <= '1';
|
o.lock <= '1';
|
o.sel <= (others => '1');
|
o.sel <= (others => '1');
|
o.stb <= '1';
|
o.stb <= '1';
|
o.tga <= (others => '0');
|
o.tga <= (others => '0');
|
o.tgc <= (others => '0');
|
o.tgc <= (others => '0');
|
WAIT UNTIL falling_edge(i.clk);
|
wait until falling_edge(i.clk);
|
-- ack handling
|
-- ack handling
|
WHILE (i.ack = '0') LOOP
|
while (i.ack = '0') loop
|
WAIT UNTIL falling_edge(i.clk);
|
wait until falling_edge(i.clk);
|
END LOOP;
|
end loop;
|
read_data_o := i.dat;
|
read_data_o := i.dat;
|
WAIT UNTIL rising_edge(i.clk);
|
wait until rising_edge(i.clk);
|
o <= wb_bfm_master_out_idle_c; -- reset bus
|
o <= wb_bfm_master_out_idle_c; -- reset bus
|
END wb_read;
|
end wb_read;
|
------------------------------------------------------------------------
|
------------------------------------------------------------------------
|
------------------------------------------------------------------------
|
------------------------------------------------------------------------
|
PROCEDURE wb_read(
|
procedure wb_read(
|
address_i : IN INTEGER;
|
address_i : in integer;
|
expected_data_i : IN INTEGER;
|
expected_data_i : in integer;
|
SIGNAL i : IN wishbone_bfm_master_in_t;
|
signal i : in wishbone_bfm_master_in_t;
|
SIGNAL o : OUT wishbone_bfm_master_out_t;
|
signal o : out wishbone_bfm_master_out_t;
|
display_error_message_i : IN integer range 0 to 4 := 1;
|
display_error_message_i : in integer range 0 to 4 := 1;
|
additional_error_message_i : IN STRING := "";
|
additional_error_message_i : in string := "";
|
expected_data_mask_i : IN INTEGER := 0
|
expected_data_mask_i : in integer := 0
|
) IS
|
) is
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
VARIABLE readdata_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
|
variable readdata_v : std_logic_vector (31 downto 0);
|
VARIABLE diff_v : INTEGER;
|
variable diff_v : integer;
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
BEGIN
|
begin
|
wb_read(address_i,readdata_v,i,o); -- read from bus
|
wb_read(address_i,readdata_v,i,o); -- read from bus
|
|
|
diff_v := to_integer(readdata_v) - expected_data_i;
|
diff_v := to_integer(readdata_v) - expected_data_i;
|
|
|
IF (display_error_message_i = 1) THEN -- output errors only
|
if (display_error_message_i = 1) then -- output errors only
|
IF (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_address_width_c)) THEN
|
if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_address_width_c)) then
|
REPORT "ERROR" & additional_error_message_i & ": Expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
|
report "error" & additional_error_message_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
|
" was: 0x" & to_string(expected_data_i, 16, wishbone_address_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_address_width_c/4)
|
" was: 0x" & to_string(expected_data_i, 16, wishbone_address_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_address_width_c/4)
|
SEVERITY error;
|
severity error;
|
END IF;
|
end if;
|
ELSIF (display_error_message_i = 2) THEN -- Output all
|
elsif (display_error_message_i = 2) then -- output all
|
REPORT additional_error_message_i & ": Read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
|
report additional_error_message_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
|
" was: 0x" & to_string(readdata_v, 16, wishbone_address_width_c/4)
|
" was: 0x" & to_string(readdata_v, 16, wishbone_address_width_c/4)
|
SEVERITY note;
|
severity note;
|
ELSIF (display_error_message_i = 3) THEN -- Output Filter
|
elsif (display_error_message_i = 3) then -- output filter
|
IF ((readdata_v AND to_std_logic_vector(expected_data_mask_i, wishbone_address_width_c)) /=
|
if ((readdata_v and to_std_logic_vector(expected_data_mask_i, wishbone_address_width_c)) /=
|
to_std_logic_vector(expected_data_i, wishbone_address_width_c)) THEN
|
to_std_logic_vector(expected_data_i, wishbone_address_width_c)) then
|
REPORT additional_error_message_i & ": Read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
|
report additional_error_message_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
|
" was: 0x" & to_string(readdata_v, 16, wishbone_address_width_c/4)
|
" was: 0x" & to_string(readdata_v, 16, wishbone_address_width_c/4)
|
SEVERITY note;
|
severity note;
|
END IF;
|
end if;
|
ELSIF display_error_message_i = 4 THEN
|
elsif display_error_message_i = 4 then
|
IF (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_address_width_c)) THEN
|
if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_address_width_c)) then
|
REPORT "ERROR" & additional_error_message_i & ": Expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
|
report "error" & additional_error_message_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
|
" was: 0x" & to_string(expected_data_i, 16, wishbone_address_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_address_width_c/4) & " Diff: " & to_string(readdata_v,16,wishbone_address_width_c/4)
|
" was: 0x" & to_string(expected_data_i, 16, wishbone_address_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_address_width_c/4) & " diff: " & to_string(readdata_v,16,wishbone_address_width_c/4)
|
SEVERITY error;
|
severity error;
|
END IF;
|
end if;
|
END IF;
|
end if;
|
END wb_read;
|
end wb_read;
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
end package body;
|
end package body;
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
---- end of file ----
|
---- end of file ----
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
No newline at end of file
|
No newline at end of file
|
