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[/] [vhdl_wb_tb/] [trunk/] [rtl/] [vhdl/] [core_top.vhd] - Diff between revs 2 and 4

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----                                                              ---- 
----                                                              ---- 
----  To Do:                                                      ---- 
----  To Do:                                                      ---- 
----   -                                                          ---- 
----   -                                                          ---- 
----                                                              ---- 
----                                                              ---- 
----  Author(s):                                                  ---- 
----  Author(s):                                                  ---- 
----      - Sinx, email@opencores.org               ---- 
----      - Sinx, sinx@opencores.org                              ---- 
----                                                              ---- 
----                                                              ---- 
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--    SVN information
----    SVN information
--
----
--      $URL:  $
----      $URL:  $
-- $Revision:  $
---- $Revision:  $
--     $Date:  $
----     $Date:  $
--   $Author:  $
----   $Author:  $
--       $Id:  $
----       $Id:  $
--
 
---------------------------------------------------------------------- 
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----                                                              ---- 
----                                                              ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
----                                                              ---- 
----                                                              ---- 
---- This source file may be used and distributed without         ---- 
---- This source file may be used and distributed without         ---- 
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    signals_i                       : in std_logic_vector(g_number_of_in_signals-1 downto 0);
    signals_i                       : in std_logic_vector(g_number_of_in_signals-1 downto 0);
    signals_o                       : out std_logic_vector(g_number_of_out_signals-1 downto 0)
    signals_o                       : out std_logic_vector(g_number_of_out_signals-1 downto 0)
    );
    );
end core_top;
end core_top;
 
 
--=architecture===============================================================
-- architecture ------------------------------------------------------
architecture rtl of core_top is
architecture rtl of core_top is
  --============================================================================
  ------------------------------------------------------------------------------
  -- signal declaration
  -- signal declaration
  --============================================================================
  ------------------------------------------------------------------------------
  signal    shift_register_r   : std_logic_vector (g_number_of_out_signals-1 downto 0);
  signal    shift_register_r   : std_logic_vector (g_number_of_out_signals-1 downto 0);
  signal    old_shift_clock_r  : std_logic := '0';
  signal    old_shift_clock_r  : std_logic := '0';
  --============================================================================
  ------------------------------------------------------------------------------
begin
begin
  ------------------------------------------------------------------------------
  ------------------------------------------------------------------------------
  -- module instantiation
  -- module instantiation
  ------------------------------------------------------------------------------
  ------------------------------------------------------------------------------
  proc_shift_register : process (all)
  proc_shift_register : process (all)
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      end if;
      end if;
    end process;
    end process;
  ------------------------------------------------------------------------------
  ------------------------------------------------------------------------------
  signals_o <= shift_register_r;
  signals_o <= shift_register_r;
  ------------------------------------------------------------------------------
  ------------------------------------------------------------------------------
  ------------------------------------------------------------------------------
 
  ------------------------------------------------------------------------------
 
  ------------------------------------------------------------------------------
 
--============================================================================
 
end rtl; --core_top
 
--============================================================================
 
-- end of file
 
--============================================================================
 
 
 
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end rtl;
 
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