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Line 61... |
use work.wishbone_pkg.all;
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use work.wishbone_pkg.all;
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|
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-- entity ------------------------------------------------------------
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-- entity ------------------------------------------------------------
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entity core_top is
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entity core_top is
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generic(
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generic(
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g_number_of_in_signals : natural := 1;
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number_of_in_signals_g : natural := 1;
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g_number_of_out_signals : natural := 1
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number_of_out_signals_g : natural := 1
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);
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);
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port(
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port(
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clock_i : in std_logic;
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clock_i : in std_logic;
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reset_i : in std_logic;
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reset_i : in std_logic;
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signals_i : in std_logic_vector(g_number_of_in_signals-1 downto 0);
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signals_i : in std_logic_vector(number_of_in_signals_g-1 downto 0);
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signals_o : out std_logic_vector(g_number_of_out_signals-1 downto 0)
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signals_o : out std_logic_vector(number_of_out_signals_g-1 downto 0)
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);
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);
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end core_top;
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end core_top;
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-- architecture ------------------------------------------------------
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-- architecture ------------------------------------------------------
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architecture rtl of core_top is
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architecture rtl of core_top is
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- signal declaration
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-- signal declaration
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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signal shift_register_r : std_logic_vector (g_number_of_out_signals-1 downto 0);
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signal shift_register_r : std_logic_vector (number_of_out_signals_g-1 downto 0);
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signal old_shift_clock_r : std_logic := '0';
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signal old_shift_clock_r : std_logic := '0';
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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begin
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begin
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- module instantiation
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-- module instantiation
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