OpenCores
URL https://opencores.org/ocsvn/vhdl_wb_tb/vhdl_wb_tb/trunk

Subversion Repositories vhdl_wb_tb

[/] [vhdl_wb_tb/] [trunk/] [rtl/] [vhdl/] [packages/] [my_project_pkg.vhd] - Diff between revs 14 and 27

Show entire file | Details | Blame | View Log

Rev 14 Rev 27
Line 15... Line 15...
----                                                              ---- 
----                                                              ---- 
---------------------------------------------------------------------- 
---------------------------------------------------------------------- 
----    SVN information
----    SVN information
----
----
----      $URL: file:///svn/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl/vhdl/packages/my_project_pkg.vhd $
----      $URL: file:///svn/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl/vhdl/packages/my_project_pkg.vhd $
---- $Revision: 14 $
---- $Revision: 27 $
----     $Date: 2018-07-22 16:27:41 +0200 (Sun, 22 Jul 2018) $
----     $Date: 2019-09-21 17:20:11 +0200 (Sat, 21 Sep 2019) $
----   $Author: sinx $
----   $Author: sinx $
----       $Id: my_project_pkg.vhd 14 2018-07-22 14:27:41Z sinx $
----       $Id: my_project_pkg.vhd 27 2019-09-21 15:20:11Z sinx $
---------------------------------------------------------------------- 
---------------------------------------------------------------------- 
----                                                              ---- 
----                                                              ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
----                                                              ---- 
----                                                              ---- 
---- This source file may be used and distributed without         ---- 
---- This source file may be used and distributed without         ---- 
Line 55... Line 55...
 
 
-- package -----------------------------------------------------------
-- package -----------------------------------------------------------
package my_project_pkg is
package my_project_pkg is
 
 
  constant wishbone_address_width_c : integer := 32;
  constant wishbone_address_width_c : integer := 32;
 
  constant wishbone_unused_address_c : std_logic_vector(wishbone_address_width_c-1 DOWNTO 0) := X"DEADDEAD"; -- "X" might lead to less resources. Meaningful value might ease debugging
  constant wishbone_data_width_c    : integer := 32;
  constant wishbone_data_width_c    : integer := 32;
  constant wishbone_data_of_unused_address_c : std_logic_vector(wishbone_data_width_c-1 DOWNTO 0) := X"DEADDEAD"; -- "X" might lead to less resources. Meaningful value might ease debugging
  constant wishbone_data_of_unused_address_c : std_logic_vector(wishbone_data_width_c-1 DOWNTO 0) := X"DEADDEAD"; -- "X" might lead to less resources. Meaningful value might ease debugging
 
 
  constant exit_simulator_at_tc_end_c        : std_logic_vector := "0"; -- "1": exit simulator at end of tc_xxxx file. used for scripted simulation runs; 
  constant exit_simulator_at_tc_end_c        : std_logic_vector := "0"; -- "1": exit simulator at end of tc_xxxx file. used for scripted simulation runs; 
                                                                        -- "0": just pause simulator at end of tc_xxx file. used for manual simulation runs.
                                                                        -- "0": just pause simulator at end of tc_xxx file. used for manual simulation runs.

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.