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[/] [vhdl_wb_tb/] [trunk/] [rtl/] [vhdl/] [packages/] [my_project_pkg.vhd] - Diff between revs 2 and 4

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---------------------------------------------------------------------- 
----                                                              ---- 
----                                                              ---- 
----  WISHBONE XXX IP Core                                        ---- 
----  VHDL Wishbone TESTBENCH                                     ---- 
----                                                              ---- 
----                                                              ---- 
----  This file is part of the XXX project                        ---- 
----  This file is part of the vhdl_wb_tb project                 ---- 
----  http://www.opencores.org/cores/xxx/                         ---- 
----  http://www.opencores.org/cores/vhdl_wb_tb/                  ---- 
----                                                              ---- 
----                                                              ---- 
----  Description                                                 ---- 
----  This file contains the project specific defines             ----
----  Implementation of XXX IP core according to                  ---- 
 
----  XXX IP core specification document.                         ---- 
 
----                                                              ---- 
----                                                              ---- 
----  To Do:                                                      ---- 
----  To Do:                                                      ---- 
----   - Adjust and rename this package for your project          ---- 
----   -                                                          ---- 
----   - remove these comments                                    ---- 
 
----                                                              ---- 
----                                                              ---- 
----  Author(s):                                                  ---- 
----  Author(s):                                                  ---- 
----      - First & Last Name, email@opencores.org                ---- 
----      - Sinx, sinx@opencores.org                              ---- 
----                                                              ---- 
----                                                              ---- 
----------------------------------------------------------------------
----------------------------------------------------------------------
--    SVN information
----    SVN information
--
----
--      $URL:  $
----      $URL:  $
-- $Revision:  $
---- $Revision:  $
--     $Date:  $
----     $Date:  $
--   $Author:  $
----   $Author:  $
--       $Id:  $
----       $Id:  $
--
 
---------------------------------------------------------------------- 
---------------------------------------------------------------------- 
----                                                              ---- 
----                                                              ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
----                                                              ---- 
----                                                              ---- 
---- This source file may be used and distributed without         ---- 
---- This source file may be used and distributed without         ---- 
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---- You should have received a copy of the GNU Lesser General    ---- 
---- You should have received a copy of the GNU Lesser General    ---- 
---- Public License along with this source; if not, download it   ---- 
---- Public License along with this source; if not, download it   ---- 
---- from http://www.opencores.org/lgpl.shtml                     ---- 
---- from http://www.opencores.org/lgpl.shtml                     ---- 
----                                                              ---- 
----                                                              ---- 
----------------------------------------------------------------------
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-- library -----------------------------------------------------------
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.numeric_std.all;
 
 
library work;
library work;
 
 
 
-- package -----------------------------------------------------------
package my_project_pkg is
package my_project_pkg is
 
 
  constant wishbone_address_width_c : integer := 32;
  constant wishbone_address_width_c : integer := 32;
  constant wishbone_data_width_c    : integer := 32;
  constant wishbone_data_width_c    : integer := 32;
  constant wishbone_data_of_unused_address_c : std_logic_vector(wishbone_data_width_c-1 DOWNTO 0) := X"DEADDEAD"; -- "X" might lead to less resources. Meaningful value might ease debugging
  constant wishbone_data_of_unused_address_c : std_logic_vector(wishbone_data_width_c-1 DOWNTO 0) := X"DEADDEAD"; -- "X" might lead to less resources. Meaningful value might ease debugging
  constant wishbone_data_of_unused_address_p : std_logic_vector(wishbone_data_width_c-1 DOWNTO 0) := X"DEADBEEF"; -- "X" might lead to less resources. Meaningful value might ease debugging
 
 
  constant exit_simulator_at_tc_end_c        : std_logic_vector := "0"; -- "1": exit simulator at end of tc_xxxx file. used for scripted simulation runs; 
 
                                                                        -- "0": just pause simulator at end of tc_xxx file. used for manual simulation runs.
 
 
  subtype wishbone_tag_data_t is std_logic_vector(1 downto 0);
  subtype wishbone_tag_data_t is std_logic_vector(1 downto 0);
  subtype wishbone_tag_address_t is std_logic_vector(1 downto 0);
  subtype wishbone_tag_address_t is std_logic_vector(1 downto 0);
  subtype wishbone_tag_cycle_t is std_logic_vector(1 downto 0);
  subtype wishbone_tag_cycle_t is std_logic_vector(1 downto 0);
 
 
  --type t_wishbone_interface_mode is (CLASSIC, PIPELINED);
  --type t_wishbone_interface_mode is (CLASSIC, PIPELINED);
  --type t_wishbone_address_granularity is (BYTE, WORD);
  --type t_wishbone_address_granularity is (BYTE, WORD);
  constant zero_c : std_logic_vector(511 downto 0) := (others => '0');
  constant zero_c : std_logic_vector(511 downto 0) := (others => '0');
end my_project_pkg;
end my_project_pkg;
 
 
 
-- package body ------------------------------------------------------
package body my_project_pkg is
package body my_project_pkg is
end my_project_pkg;
end my_project_pkg;
 
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---- end of file                                                  ---- 
 
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