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[/] [vhdl_wb_tb/] [trunk/] [rtl/] [vhdl/] [packages/] [my_project_pkg.vhd] - Diff between revs 4 and 5

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Rev 4 Rev 5
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  subtype wishbone_tag_data_t is std_logic_vector(1 downto 0);
 
  subtype wishbone_tag_data_t is std_logic_vector(1 downto 0);
 
  subtype wishbone_tag_address_t is std_logic_vector(1 downto 0);
 
  subtype wishbone_tag_address_t is std_logic_vector(1 downto 0);
 
  subtype wishbone_tag_cycle_t is std_logic_vector(1 downto 0);
 
  subtype wishbone_tag_cycle_t is std_logic_vector(1 downto 0);
 
 
 
 
 
  --type t_wishbone_interface_mode is (CLASSIC, PIPELINED);
 
  --type wishbone_interface_mode_t is (CLASSIC, PIPELINED);
 
  --type t_wishbone_address_granularity is (BYTE, WORD);
 
  --type wishbone_address_granularity_t is (BYTE, WORD);
 
  constant zero_c : std_logic_vector(511 downto 0) := (others => '0');
 
  constant zero_c : std_logic_vector(511 downto 0) := (others => '0');
 
end my_project_pkg;
 
end my_project_pkg;
 
 
 
 
 
-- package body ------------------------------------------------------
 
-- package body ------------------------------------------------------
 
package body my_project_pkg is
 
package body my_project_pkg is

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