OpenCores
URL https://opencores.org/ocsvn/vhdl_wb_tb/vhdl_wb_tb/trunk

Subversion Repositories vhdl_wb_tb

[/] [vhdl_wb_tb/] [trunk/] [rtl/] [vhdl/] [packages/] [wishbone_pkg.vhd] - Diff between revs 22 and 25

Show entire file | Details | Blame | View Log

Rev 22 Rev 25
Line 21... Line 21...
----                                                              ----
----                                                              ----
----------------------------------------------------------------------
----------------------------------------------------------------------
----    SVN information
----    SVN information
----
----
----      $URL: file:///svn/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl/vhdl/packages/wishbone_pkg.vhd $
----      $URL: file:///svn/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl/vhdl/packages/wishbone_pkg.vhd $
---- $Revision: 22 $
---- $Revision: 25 $
----     $Date: 2018-08-01 12:06:31 +0200 (Wed, 01 Aug 2018) $
----     $Date: 2018-08-03 13:05:57 +0200 (Fri, 03 Aug 2018) $
----   $Author: sinx $
----   $Author: sinx $
----       $Id: wishbone_pkg.vhd 22 2018-08-01 10:06:31Z sinx $
----       $Id: wishbone_pkg.vhd 25 2018-08-03 11:05:57Z sinx $
----------------------------------------------------------------------
----------------------------------------------------------------------
----                                                              ----
----                                                              ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ----
----                                                              ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- This source file may be used and distributed without         ----
Line 115... Line 115...
  constant wb_master_out_idle_c : wishbone_master_out_t := (
  constant wb_master_out_idle_c : wishbone_master_out_t := (
                                                        clk  =>  '0',
                                                        clk  =>  '0',
                                                        dat  =>  wishbone_data_of_unused_address_c,
                                                        dat  =>  wishbone_data_of_unused_address_c,
                                                        rst  =>  '0',
                                                        rst  =>  '0',
                                                        tgd  =>  (others=>'0'),
                                                        tgd  =>  (others=>'0'),
                                                        adr  =>  (others=>'U'),
    adr  =>  wishbone_unused_address_c, -- do not use 'X','U','Z','H','L', since this will generate warnings in address decoders where to_integer() is used
                                                        cyc  =>  '0',
                                                        cyc  =>  '0',
                                                        lock =>  '0',
                                                        lock =>  '0',
                                                        sel  =>  (others=>'0'),
                                                        sel  =>  (others=>'0'),
                                                        stb  =>  '0',
                                                        stb  =>  '0',
                                                        tga  =>  (others=>'0'),
                                                        tga  =>  (others=>'0'),

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.