| Line 1... |
Line 1... |
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
---- ----
|
---- ----
|
---- VHDL Wishbone TESTBENCH ----
|
---- VHDL Wishbone TESTBENCH ----
|
---- ----
|
---- ----
|
---- This file is part of the vhdl_wb_tb project ----
|
---- This file is part of the vhdl_wb_tb project ----
|
---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
|
---- https://opencores.org/project/vhdl_wb_tb ----
|
---- ----
|
---- ----
|
---- This file contains the highest (top) module of the test ----
|
---- This file contains the highest (top) module for synthesis. ----
|
---- bench. ----
|
---- Like tb_top it instantiates the core_top module and ----
|
---- It instantiates the design under test (DUT), instantiates ----
|
---- provides parameters/generics. Where the tb_top module ----
|
---- the stimulator module for test vector generation, ----
|
---- provides parameters for simulation this file provides ----
|
---- instantiates the verifier module for result comparison, ----
|
---- parameters for synthesis. ----
|
---- instantiates the test case top (testcase_top) bfm, ----
|
|
---- interconnects all three components, generates DUT-external ----
|
|
---- clocks and resets. ----
|
|
---- ----
|
---- ----
|
---- To Do: ----
|
---- To Do: ----
|
---- - ----
|
---- - ----
|
---- ----
|
---- ----
|
---- Author(s): ----
|
---- Author(s): ----
|
---- - Sinx, email@opencores.org ----
|
---- - Sinx, sinx@opencores.org ----
|
---- ----
|
---- ----
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
-- SVN information
|
---- SVN information
|
--
|
----
|
-- $URL: $
|
---- $URL: $
|
-- $Revision: $
|
---- $Revision: $
|
-- $Date: $
|
---- $Date: $
|
-- $Author: $
|
---- $Author: $
|
-- $Id: $
|
---- $Id: $
|
--
|
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
---- ----
|
---- ----
|
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
|
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
|
---- ----
|
---- ----
|
---- This source file may be used and distributed without ----
|
---- This source file may be used and distributed without ----
|
| Line 71... |
Line 67... |
signals_i : in std_logic_vector(7 downto 0);
|
signals_i : in std_logic_vector(7 downto 0);
|
signals_o : out std_logic_vector(7 downto 0)
|
signals_o : out std_logic_vector(7 downto 0)
|
);
|
);
|
end entity top;
|
end entity top;
|
|
|
--=architecture===============================================================
|
-- architecture ------------------------------------------------------
|
architecture rtl of top is
|
architecture rtl of top is
|
--============================================================================
|
-----------------------------------------------------------------------------
|
-- signal declaration
|
|
--============================================================================
|
|
-- constant number_of_stimulus_signals_c : integer := 8;
|
-- constant number_of_stimulus_signals_c : integer := 8;
|
-- signal s_verify : std_logic_vector(number_of_verify_signals_c-1 downto 0);
|
-- signal s_verify : std_logic_vector(number_of_verify_signals_c-1 downto 0);
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
begin
|
begin
|
--============================================================================
|
-----------------------------------------------------------------------------
|
-- instance of design
|
-- instance of design
|
core_top_inst : entity work.core_top
|
core_top_inst : entity work.core_top
|
generic map(
|
generic map(
|
g_number_of_in_signals => 8,
|
g_number_of_in_signals => 8,
|
g_number_of_out_signals => 8
|
g_number_of_out_signals => 8
|
| Line 95... |
Line 89... |
signals_i => signals_i,
|
signals_i => signals_i,
|
signals_o => signals_o
|
signals_o => signals_o
|
);
|
);
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
end rtl;
|
end rtl;
|
--============================================================================
|
|
-- end of file
|
|
--============================================================================
|
|
No newline at end of file
|
No newline at end of file
|
|
----------------------------------------------------------------------
|
|
---- end of file ----
|
|
----------------------------------------------------------------------
|
No newline at end of file
|
No newline at end of file
|
