URL https://opencores.org/ocsvn/vhdl_wb_tb/vhdl_wb_tb/trunk

Subversion Repositories vhdl_wb_tb

[/] [vhdl_wb_tb/] [trunk/] [rtl_sim/] [run/] [sim.mpf] - Diff between revs 6 and 24

Rev 6	Rev 24
Line 167...	Line 167...
`; %T - Time of assertion`	`; %T - Time of assertion`
`; %D - Delta`	`; %D - Delta`
`; %I - Instance or Region pathname (if available)`	`; %I - Instance or Region pathname (if available)`
`; %% - print '%' character`	`; %% - print '%' character`
`; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"`	`; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"`
`AssertionFormat = "** [%I] %T %S %R\n"`	`AssertionFormat = "** %T %S %R\n"`

`; Assertion File - alternate file for storing VHDL/Verilog assertion messages`	`; Assertion File - alternate file for storing VHDL/Verilog assertion messages`
`; AssertFile = assert.log`	`; AssertFile = assert.log`

`; Default radix for all windows and commands...`	`; Default radix for all windows and commands...`