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Line 62... |
// 5 FDCBgrp (indexed bit banging)
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// 5 FDCBgrp (indexed bit banging)
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//
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//
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//
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//
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//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0
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//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0
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//
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//
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// $Id: opcodes.v,v 1.3 2004-05-21 02:51:25 bporcella Exp $
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// $Id: opcodes.v,v 1.4 2004-05-27 14:23:36 bporcella Exp $
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//
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//
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// $Date: 2004-05-21 02:51:25 $
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// $Date: 2004-05-27 14:23:36 $
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// $Revision: 1.3 $
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// $Revision: 1.4 $
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// $Author: bporcella $
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// $Author: bporcella $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2004/05/21 02:51:25 bporcella
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// inst test got to the worked macro
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//
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// Revision 1.2 2004/05/18 22:31:20 bporcella
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// Revision 1.2 2004/05/18 22:31:20 bporcella
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// instruction test getting to final stages
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// instruction test getting to final stages
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//
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//
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// Revision 1.1 2004/04/17 18:26:06 bporcella
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// Revision 1.1 2004/04/17 18:26:06 bporcella
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// put this here to try an end-run around lint mikefile problem
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// put this here to try an end-run around lint mikefile problem
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Line 428... |
Line 431... |
ED_ADCsHL_REG = 8'b1001__1010, // compair with {ir[9:6],ir[3:0]}
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ED_ADCsHL_REG = 8'b1001__1010, // compair with {ir[9:6],ir[3:0]}
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ED_LDs6NN7_REG = 8'b1001__0011, // compair with {ir[9:6],ir[3:0]} REG = BC,DE,HL,SP
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ED_LDs6NN7_REG = 8'b1001__0011, // compair with {ir[9:6],ir[3:0]} REG = BC,DE,HL,SP
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ED_LDsREG_6NN7 = 8'b1001__1011, // compair with {ir[9:6],ir[3:0]} REG = BC,DE,HL,SP
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ED_LDsREG_6NN7 = 8'b1001__1011, // compair with {ir[9:6],ir[3:0]} REG = BC,DE,HL,SP
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ED_NEG = 7'b1001___100, // compair with {ir[9:6],ir[2:0]} all A<= -A
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ED_NEG = 7'b1001___100, // compair with {ir[9:6],ir[2:0]} all A<= -A
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ED_RETN = 7'b1001___101, // compair with {ir[9:6],ir[2:0]} and !reti
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ED_RETN = 7'b1001___101, // compair with {ir[9:6],ir[2:0]} and !reti
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ED_RETI = 10'h24D,
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DBL_REG_BC = 2'b00, // compair with ir[5:4]
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DBL_REG_BC = 2'b00, // compair with ir[5:4]
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DBL_REG_DE = 2'b01, // compair with ir[5:4]
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DBL_REG_DE = 2'b01, // compair with ir[5:4]
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DBL_REG_HL = 2'b10, // compair with ir[5:4]
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DBL_REG_HL = 2'b10, // compair with ir[5:4]
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DBL_REG_SP = 2'b11, // compair with ir[5:4]
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DBL_REG_SP = 2'b11, // compair with ir[5:4]
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