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[/] [wb_z80/] [trunk/] [rtl/] [opcodes.v] - Diff between revs 27 and 32

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Rev 27 Rev 32
Line 40... Line 40...
//
//
// The purpose of the origiional file was to aid in low level z80 software debug.
// The purpose of the origiional file was to aid in low level z80 software debug.
// Here, we are trying to make the parameters we use for instruction decoding
// Here, we are trying to make the parameters we use for instruction decoding
// as easy to understand as possible.
// as easy to understand as possible.
//
//
// The origional file is included as a comment below.  (this is a very long file)
 
// It is then re-produced with transformations --  so the significance of the parameters should 
 
// be very clear.
 
//
//
// Note how assembler syntax is transformed 
// Note how assembler syntax is transformed 
// into verilog symbols.    
// into verilog symbols.    
// 
// 
//
//
Line 62... Line 59...
//    5  FDCBgrp   (indexed bit banging)
//    5  FDCBgrp   (indexed bit banging)
//
//
//
//
//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0
//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0
//
//
//  $Id: opcodes.v,v 1.4 2004-05-27 14:23:36 bporcella Exp $
//  $Id: opcodes.v,v 1.5 2007-10-02 20:25:12 bporcella Exp $
//
//
//  $Date: 2004-05-27 14:23:36 $
//  $Date: 2007-10-02 20:25:12 $
//  $Revision: 1.4 $
//  $Revision: 1.5 $
//  $Author: bporcella $
//  $Author: bporcella $
//  $Locker:  $
//  $Locker:  $
//  $State: Exp $
//  $State: Exp $
//
//
// Change History:
// Change History:
//      $Log: not supported by cvs2svn $
//      $Log: not supported by cvs2svn $
 
//      Revision 1.4  2004/05/27 14:23:36  bporcella
 
//      Instruction test (with interrupts) runs!!!
 
//
//      Revision 1.3  2004/05/21 02:51:25  bporcella
//      Revision 1.3  2004/05/21 02:51:25  bporcella
//      inst test  got to the worked macro
//      inst test  got to the worked macro
//
//
//      Revision 1.2  2004/05/18 22:31:20  bporcella
//      Revision 1.2  2004/05/18 22:31:20  bporcella
//      instruction test getting to final stages
//      instruction test getting to final stages

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