Line 40... |
Line 40... |
//
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//
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// The purpose of the origiional file was to aid in low level z80 software debug.
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// The purpose of the origiional file was to aid in low level z80 software debug.
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// Here, we are trying to make the parameters we use for instruction decoding
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// Here, we are trying to make the parameters we use for instruction decoding
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// as easy to understand as possible.
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// as easy to understand as possible.
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//
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//
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// The origional file is included as a comment below. (this is a very long file)
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// It is then re-produced with transformations -- so the significance of the parameters should
|
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// be very clear.
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//
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//
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// Note how assembler syntax is transformed
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// Note how assembler syntax is transformed
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// into verilog symbols.
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// into verilog symbols.
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//
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//
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//
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//
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Line 62... |
Line 59... |
// 5 FDCBgrp (indexed bit banging)
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// 5 FDCBgrp (indexed bit banging)
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//
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//
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//
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//
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//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0
|
//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0
|
//
|
//
|
// $Id: opcodes.v,v 1.4 2004-05-27 14:23:36 bporcella Exp $
|
// $Id: opcodes.v,v 1.5 2007-10-02 20:25:12 bporcella Exp $
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//
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//
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// $Date: 2004-05-27 14:23:36 $
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// $Date: 2007-10-02 20:25:12 $
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// $Revision: 1.4 $
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// $Revision: 1.5 $
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// $Author: bporcella $
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// $Author: bporcella $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
|
// $State: Exp $
|
//
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//
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// Change History:
|
// Change History:
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.4 2004/05/27 14:23:36 bporcella
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// Instruction test (with interrupts) runs!!!
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//
|
// Revision 1.3 2004/05/21 02:51:25 bporcella
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// Revision 1.3 2004/05/21 02:51:25 bporcella
|
// inst test got to the worked macro
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// inst test got to the worked macro
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//
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//
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// Revision 1.2 2004/05/18 22:31:20 bporcella
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// Revision 1.2 2004/05/18 22:31:20 bporcella
|
// instruction test getting to final stages
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// instruction test getting to final stages
|