///////////////////////////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// file name: z80_testbed.v ////
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//// file name: z80_testbed.v ////
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//// description: testbed for Wishbone z80 ////
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//// description: testbed for Wishbone z80 ////
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//// project: wb_z80 ////
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//// project: wb_z80 ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author: B.J. Porcella ////
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//// Author: B.J. Porcella ////
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//// bporcella@sbcglobal.net ////
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//// bporcella@sbcglobal.net ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// ////
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///////////////////////////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000-2002 B.J. Porcella ////
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//// Copyright (C) 2000-2002 B.J. Porcella ////
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//// Real Time Solutions ////
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//// Real Time Solutions ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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///////////////////////////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: z80_testbed.v,v 1.5 2007-10-02 20:25:12 bporcella Exp $
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// $Id: z80_testbed.v,v 1.5 2007-10-02 20:25:12 bporcella Exp $
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//
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//
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// $Date: 2007-10-02 20:25:12 $
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// $Date: 2007-10-02 20:25:12 $
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// $Revision: 1.5 $
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// $Revision: 1.5 $
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// $Author: bporcella $
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// $Author: bporcella $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2004/05/27 14:25:04 bporcella
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// Revision 1.4 2004/05/27 14:25:04 bporcella
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// Instruction test (with interrupts) runs!!!
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// Instruction test (with interrupts) runs!!!
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//
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//
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// Revision 1.3 2004/05/21 02:51:25 bporcella
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// Revision 1.3 2004/05/21 02:51:25 bporcella
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// inst test got to the worked macro
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// inst test got to the worked macro
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//
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//
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// Revision 1.2 2004/05/18 22:31:21 bporcella
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// Revision 1.2 2004/05/18 22:31:21 bporcella
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// instruction test getting to final stages
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// instruction test getting to final stages
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//
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//
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// Revision 1.1 2004/05/13 14:57:35 bporcella
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// Revision 1.1 2004/05/13 14:57:35 bporcella
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// testbed files
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// testbed files
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//
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//
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// Revision 1.1.1.1 2004/04/13 23:47:42 bporcella
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// Revision 1.1.1.1 2004/04/13 23:47:42 bporcella
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// import first files
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// import first files
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//
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//
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//
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//
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//
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//
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//-------1---------2---------3--------Module Name and Port List------7---------8---------9--------0
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//-------1---------2---------3--------Module Name and Port List------7---------8---------9--------0
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`timescale 1ns/10ps
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`timescale 1ns/10ps
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`define COMPILE_BIST // need this for this file to work
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`define COMPILE_BIST // need this for this file to work
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// testbench - do not synthesize. this just sequences the bist signals
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// testbench - do not synthesize. this just sequences the bist signals
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module z80_testbed();
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module z80_testbed();
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reg rst, bist_req, clk;
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reg rst, bist_req, clk;
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wire bist_ack;
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wire bist_ack;
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wire bist_err;
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wire bist_err;
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//------- CAUTION TEST RESULTS DEPEND ON INITIAL CONDITIONS -------
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//------- CAUTION TEST RESULTS DEPEND ON INITIAL CONDITIONS -------
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// bist will not pass if some of these inputs are not as specified.
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// bist will not pass if some of these inputs are not as specified.
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//
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//
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z80_core_top i_z80_core_top(
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z80_core_top i_z80_core_top(
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.wb_dat_o(),
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.wb_dat_o(),
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.wb_stb_o(),
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.wb_stb_o(),
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.wb_cyc_o(),
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.wb_cyc_o(),
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.wb_we_o(),
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.wb_we_o(),
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.wb_adr_o(),
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.wb_adr_o(),
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.wb_tga_o(),
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.wb_tga_o(),
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.wb_ack_i(1'b0),
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.wb_ack_i(1'b0),
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.wb_clk_i(clk),
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.wb_clk_i(clk),
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.wb_dat_i(8'h0),
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.wb_dat_i(8'h0),
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.wb_rst_i(rst),
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.wb_rst_i(rst),
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.bist_ack_o(bist_ack),
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.bist_ack_o(bist_ack),
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.bist_err_o(bist_err),
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.bist_err_o(bist_err),
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.bist_req_i(bist_req),
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.bist_req_i(bist_req),
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.int_req_i(1'b0) //
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.int_req_i(1'b0) //
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);
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);
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initial
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initial
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begin
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begin
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clk = 0;
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clk = 0;
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// timeout if u hang up -- always a good idea.
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// timeout if u hang up -- always a good idea.
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#500000 $finish;
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#500000 $finish;
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$display("simulation timeout");
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$display("simulation timeout");
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end
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end
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always #5 clk = ~clk;
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always #5 clk = ~clk;
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// The bist sequencer --- pertty trivial
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// The bist sequencer --- pertty trivial
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initial
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initial
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begin
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begin
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rst = 1'b0;
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rst = 1'b0;
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bist_req = 1'b0;
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bist_req = 1'b0;
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@( posedge clk) rst = 1'b1;
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@( posedge clk) rst = 1'b1;
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@( posedge clk) rst = 1'b0;
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@( posedge clk) rst = 1'b0;
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@( posedge clk) bist_req = 1'b1;
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@( posedge clk) bist_req = 1'b1;
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@( bist_ack ) ;
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@( bist_ack ) ;
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@( posedge clk)
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@( posedge clk)
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if ( bist_err ) $display("TB bist error");
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if ( bist_err ) $display("TB bist error");
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else $display( "TB bist ok" );
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else $display( "TB bist ok" );
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$finish;
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$finish;
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end
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end
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initial
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initial
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begin
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begin
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$dumpfile("dump.vcd");
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$dumpfile("dump.vcd");
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$dumpvars;
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$dumpvars;
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end
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end
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