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[/] [xulalx25soc/] [trunk/] [rtl/] [wbubus.v] - Diff between revs 46 and 102

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////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Filename:    wbubus.v
// Filename:    wbubus.v
//
//
// Project:     XuLA2 board
// Project:     FPGA library
//
//
// Purpose:     This is the top level file for the entire JTAG-USB to Wishbone
// Purpose:     This is the top level file for the entire JTAG-USB to Wishbone
//              bus conversion.  (It's also the place to start debugging, should
//              bus conversion.  (It's also the place to start debugging, should
//      things not go as planned.)  Bytes come into this routine, bytes go out,
//      things not go as planned.)  Bytes come into this routine, bytes go out,
//      and the wishbone bus (external to this routine) is commanded in between.
//      and the wishbone bus (external to this routine) is commanded in between.
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// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
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//
//
module  wbubus(i_clk, i_rx_stb, i_rx_data,
module  wbubus(i_clk, i_rx_stb, i_rx_data,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                i_wb_ack, i_wb_stall, i_wb_err, i_wb_data,
                i_wb_ack, i_wb_stall, i_wb_err, i_wb_data,
                i_interrupt,
                i_interrupt,
                o_tx_stb, o_tx_data, i_tx_busy);
                o_tx_stb, o_tx_data, i_tx_busy, o_dbg);
        parameter       LGWATCHDOG=19;
        parameter       LGWATCHDOG=19;
        input                   i_clk;
        input                   i_clk;
        input                   i_rx_stb;
        input                   i_rx_stb;
        input           [7:0]    i_rx_data;
        input           [7:0]    i_rx_data;
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
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        input           [31:0]   i_wb_data;
        input           [31:0]   i_wb_data;
        input                   i_interrupt;
        input                   i_interrupt;
        output  wire            o_tx_stb;
        output  wire            o_tx_stb;
        output  wire    [7:0]    o_tx_data;
        output  wire    [7:0]    o_tx_data;
        input                   i_tx_busy;
        input                   i_tx_busy;
        // output       wire    [31:0]  o_dbg;
        output  wire            o_dbg;
 
 
 
 
        reg             r_wdt_reset;
        reg             r_wdt_reset;
 
 
        // Decode ASCII input requests into WB bus cycle requests
        // Decode ASCII input requests into WB bus cycle requests
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        assign  cyc_debug = { 1'b0, o_wb_cyc, o_wb_stb, o_wb_we, i_wb_ack, i_wb_stall,
        assign  cyc_debug = { 1'b0, o_wb_cyc, o_wb_stb, o_wb_we, i_wb_ack, i_wb_stall,
                                (i_wb_err||r_wdt_reset), o_wb_addr[14:0],
                                (i_wb_err||r_wdt_reset), o_wb_addr[14:0],
                                o_wb_data[4:0], i_wb_data[4:0] };
                                o_wb_data[4:0], i_wb_data[4:0] };
        assign  o_dbg = cyc_debug;
        assign  o_dbg = cyc_debug;
        */
        */
 
 
        /*
        /*
        wire    [31:0]  fif_debug;
        wire    [31:0]  fif_debug;
        assign  fif_debug = {
        assign  fif_debug = {
                        (exec_stb)&&(exec_word[35:30] == 6'h05),// 1
                        (exec_stb)&&(exec_word[35:30] == 6'h05),// 1
                        fifo_in_stb, fifo_in_word[35:30],       // 7
                        fifo_in_stb, fifo_in_word[35:30],       // 7
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                end else begin
                end else begin
                        r_wdt_timer <= r_wdt_timer+{{(LGWATCHDOG-1){1'b0}},1'b1};
                        r_wdt_timer <= r_wdt_timer+{{(LGWATCHDOG-1){1'b0}},1'b1};
                        r_wdt_reset <= 1'b0;
                        r_wdt_reset <= 1'b0;
                end
                end
 
 
 
        assign  o_dbg = w_bus_reset;
 
 
endmodule
endmodule
 
 
 
 
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