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## *ZAP* : An ARM compatible core with cache and MMU (ARMv4T ISA compatible)
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## The ZAP Soft Processor (ARMv5T Compatible)
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#### Author : Revanth Kamaraj (revanth91kamaraj@gmail.com)
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#### Author : Revanth Kamaraj (revanth91kamaraj@gmail.com)
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#### License : GPL v2
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### Description
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### Introduction
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ZAP is a pipelined ARM processor core that can execute the ARMv4T instruction
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The ZAP processor is a 10 stage pipelined processor for FPGA with support for cache and MMU (ARMv5T compliant).
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set. It is equipped with ARMv4 compatible split writeback caches and memory
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management capabilities. The processor core uses a 10 stage pipeline.
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Note that ARM GCC is included in the repository in the *sw* directory. The
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#### Features
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makefile will extract the GCC compiler into the object folder.
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### Current Status
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##### ZAP Processor (zap_top.v)
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Experimental.
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The ZAP core is a pipelined ATMv5T processor for FPGA.
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| Property | Description |
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|-----------------------|-------------------------|
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|HDL | Verilog-2001 |
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|Author | Revanth Kamaraj |
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|ARM v5T ISA Support | Fully compatible |
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|Branch Predictor | Direct mapped bimodal |
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|Write Buffer | Yes |
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|Abort Model | Base Restored |
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|Integrated v5T CP15 | Yes |
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|External Coproc. Bus | No |
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|Cache Interface | 128-Bit custom interface|
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|26-Bit Support | No |
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|L1 Code Cache | Direct mapped virtual |
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|L1 Data Cache | Direct mapped virtual |
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|Cache Write Policy | Writeback |
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|L1 Code TLB | Direct mapped |
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|L1 Data TLB | Direct mapped |
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|Bus Interface | 32-bit Wishbone B3 Linear incrementing burst |
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|Cache/TLB Lock Support | No |
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|CP15 Compliance | v5T (No fine pages) |
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|FCSE Support | Yes |
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* 10-stage pipeline design. Pipeline has bypass network to resolve dependencies. Most operations execute at a rate of 1 operation per clock.
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* 2 write ports for the register file to allow LDR/STR with writeback to execute as a single instruction.
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#### CPU Configuration (zap_top.v)
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| Parameter | Default| Description |
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|--------------------------|--------|-------------|
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| BP_ENTRIES | 1024 | Branch Predictor Settings. Predictor RAM depth. Must be 2^n and > 2 |
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| FIFO_DEPTH | 4 | Branch Predictor Settings. Command FIFO depth. Must be 2^n and > 2 |
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| STORE_BUFFER_DEPTH | 16 | Branch Predictor Settings. Depth of the store buffer. Must be 2^n and > 2 |
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| DATA_SECTION_TLB_ENTRIES | 4 | Data Cache/MMU Configuration. Section TLB entries. Must be 2^n (n > 0) |
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| DATA_LPAGE_TLB_ENTRIES | 8 | Data Cache/MMU Configuration. Large page TLB entries. Must be 2^n (n > 0) |
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| DATA_SPAGE_TLB_ENTRIES | 16 | Data Cache/MMU Configuration. Small page TLB entries. Must be 2^n (n > 0) |
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| DATA_CACHE_SIZE | 1024 | Data Cache/MMU Configuration. Cache size in bytes. Must be at least 256B and 2^n |
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| CODE_SECTION_TLB_ENTRIES | 4 | Instruction Cache/MMU Configuration. Section TLB entries. Must be 2^n (n > 0) |
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| CODE_LPAGE_TLB_ENTRIES | 8 | Instruction Cache/MMU Configuration. Large page TLB entries. Must be 2^n (n > 0) |
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| CODE_SPAGE_TLB_ENTRIES | 16 | Instruction Cache/MMU Configuration. Small page TLB entries. Must be 2^n (n > 0) |
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| CODE_CACHE_SIZE | 1024 | Instruction Cache/MMU Configuration. Cache size in bytes. Must be at least 256B and 2^n |
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### Bugs and Known Issues
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#### CPU IO Interface (zap_top.v)
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- Issues with the Thumb ISA.
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- SWAP does not bypass cache.
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### Bus Interface
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Wishbone B3 compatible 32-bit bus.
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Wishbone B3 compatible 32-bit bus.
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### Documentation
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| Dir | Size | Port | Description |
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|---------------|----------|--------------------|----------------------------------|
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Please see the PDF file at *doc/ZAP_PROCESSOR_CORE_DATASHEET.pdf*
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| input | | i_clk | Clock |
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| input | | i_reset | Reset |
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### Features
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| input | | i_irq | Interrupt. Level Sensitive. |
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| input | | i_fiq | Fast Interrupt. Level Sensitive.|
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- Fully synthesizable Verilog-2001 core.
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| output | | o_wb_cyc | Wishbone B3 Signal |
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- Store buffer for improved performance.
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| output | | o_wb_stb | WIshbone B3 signal |
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- Can execute ARMv4T code. Note that compressed instruction support is EXPERIMENTAL.
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| output | [31:0] | o_wb_adr | Wishbone B3 signal. |
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- Wishbone B3 compatible interface. Cache unit supports burst access.
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| output | | o_wb_we | Wishbone B3 signal. |
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- 10-stage pipeline design. Pipeline has bypass network to resolve dependencies.
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| output | [31:0] | o_wb_dat | Wishbone B3 signal. |
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- 2 write ports for the register file to allow LDR/STR with writeback to execute as a single instruction.
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| output | [3:0] | o_wb_sel | Wishbone B3 signal. |
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- Branch prediction supported.
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| output | [2:0] | o_wb_cti | Wishbone B3 signal. Cycle Type Indicator (Supported modes: Incrementing Burst, End of Burst)|
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- Split I and D writeback cache (Size can be configured using parameters).
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| output | [1:0] | o_wb_bte | Wishbone B3 signal. Burst Type Indicator (Supported modes: Linear) |
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- Split I and D MMUs (TLB size can be configured using parameters).
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| input | | i_wb_ack | Wishbone B3 signal. |
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- Base restored abort model to simplify data abort handling.
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| input | [31:0] | i_wb_dat | Wishbone B3 signal. |
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| output | | o_wb_stb_nxt | IGNORE THIS PORT. LEAVE OPEN. |
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### License
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| output | | o_wb_cyc_nxt | IGNORE THIS PORT. LEAVE OPEN. |
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| output | [31:0] | o_wb_adr_nxt | IGNORE THIS PORT. LEAVE OPEN. |
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(C) 2016-2018 Revanth Kamaraj.
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This program is free software; you can redistribute it and/or
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### Getting Started
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modify it under the terms of the GNU General Public License
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*Tested on Ubuntu 16.04 LTS/18.04 LTS*
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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#### Run Sample Tests
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This program is distributed in the hope that it will be useful,
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Let the variable $test_name hold the name of the test. See the src/ts directory for some basic tests pre-installed. Available test names are: factorial, arm_test, thumb_test, uart. New tests can be added using these as starting templates. Please note that these will be run on the SOC platform (chip_top) that consist of the ZAP processor, 2 x UARTs, a VIC and a timer.
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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```bash
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GNU General Public License for more details.
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sudo apt-get install sudo apt-get install gcc-arm-none-eabi binutils-arm-none-eabi gdb openocd iverilog gtkwave make perl xterm
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cd $PROJ_ROOT/src/ts/$test_name # $PROJ_ROOT is the project directory.
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You should have received a copy of the GNU General Public License
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make # Runs the test using IVerilog.
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along with this program; if not, write to the Free Software
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cd $PROJ_ROOT/obj/ts/$test_name # Switch to object folder.
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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gvim zap.log.gz # View the log file
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02110-1301, USA.
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gtkwave zap.vcd.gz # Exists if selected by Config.cfg. See PDF document for more information.
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```
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To use this processor in your SOC, instantiate this top level CPU module in your project: [CPU top file](/src/rtl/cpu/zap_top.v)
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### Implementation Specific Details
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#### FPGA Timing Performance (Vivado, Retime Enabled)
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| FPGA Part | Speed | Critical Path |
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|--------------------|-------|----------------|
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| xc7a35tiftg256-1L | 80MHz | Cache access |
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#### Coprocessor #15 Control Registers
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##### Register 0 : ID Register
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|Bits | Name | Description |
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|-----|---------|------------------------------------------|
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|31:0 | Various | Processor ID info. |
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##### Register 1 : Control
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|Bits | Name | Description |
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|-----|-----------|------------------------------------------|
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|0 | M | MMU Enable. Active high |
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|1 | A | Always 0. Alignment check off |
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|2 | D | Data Cache Enable. Active high |
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|3 | W | Always 1. Write Buffer always on. |
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|4 | P | Always 1. RESERVED |
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|5 | D | Always 1. RESERVED |
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|6 | L | Always 1. RESERVED |
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|7 | B | Always 0. Little Endian |
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|8 | S | The S bit |
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|9 | R | The R bit |
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|11 | Z | Always 1. Branch prediction enabled |
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|12 | I | Instruction Cache Enable. Active high |
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|13 | V | Normal Exception Vectors. Always 0 |
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|14 | RR | Always 1. Direct mapped cache. |
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|15 | L4 | Always 0. Normal behavior. |
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##### Register 2 : Translation Base Address
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|Bits | Name | Description |
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|-----|-----------|------------------------------------------|
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|13:0 | M | Preserve value. |
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|31:14| TTB | Upper 18-bits of translation address |
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##### Register 3 : Domain Access Control (X=0 to X=15)
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|Bits | Name | Description |
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|---------|-----------|------------------------------------------|
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|2X+1:2X | DX | DX access permission. |
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##### Register 5 : Fault Status Register
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|Bits | Name | Description |
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|-----|-----------|------------------------------------------|
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|3:0 | Status | Status. |
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|1:0 | Domain | Domain. |
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|11:8 | SBZ | Always 0. RESERVED |
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##### Register 6 : Fault Address Register
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|Bits | Name | Description |
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|-----|-----------|------------------------------------------|
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|31:0 | Addr | Fault Address. |
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##### Register 7 : Cache Functions
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| Opcode2 | CRm | Description |
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|-------------|-----------------|-------------------------------------|
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| 000 | 0111 | Flush all caches. |
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| 000 | 0101 | Flush I cache. |
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| 000 | 0110 | Flush D cache. |
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| 000 | 1011 | Clean all caches. |
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| 000 | 1010 | Clean D cache. |
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| 000 | 1111 | Clean and flush all caches. |
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| 000 | 1110 | Clean and flush D cache. |
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| Other | Other | Clean and flush ALL caches |
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##### Register 8 : TLB Functions
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|Opcode2 | CRm | Description |
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| 000 | 0111 | Flush all TLBs |
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| 000 | 0101 | Flush I TLB |
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| 000 | 0110 | Flush D TLB |
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| Other| Other | Flush all TLBs |
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##### Register 13 : FCSE Extentions
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| Field | Description |
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|-------|-------------|
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| 31:25 | PID |
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##### Lockdown Support
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* CPU memory system does not support lockdown.
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##### Tiny Pages
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* No support for tiny pages (1KB).
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