| Line 8... |
Line 8... |
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Please note that the processor is *not* an ARM clone but a completely different RTL design, written from scratch (in FPGA compliant Verilog-2001), that can run ARM v5T binaries, hence, no particular ARMX number is specified.
|
Please note that the processor is *not* an ARM clone but a completely different RTL design, written from scratch (in FPGA compliant Verilog-2001), that can run ARM v5T binaries, hence, no particular ARMX number is specified.
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|
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This project was created for the ORCONF-2016 Student Design Contest.
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This project was created for the ORCONF-2016 Student Design Contest.
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ZAP is specifically designed to work with FPGAs.
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#### Repos
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#### Repos
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GIT: https://github.com/krevanth/ZAP
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GIT: https://github.com/krevanth/ZAP
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| Line 44... |
Line 46... |
|Bus Interface | 32-bit Wishbone B3 Linear incrementing burst |
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|Bus Interface | 32-bit Wishbone B3 Linear incrementing burst |
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|Cache/TLB Lock Support | No |
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|Cache/TLB Lock Support | No |
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|CP15 Compliance | v5T (No fine pages) |
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|CP15 Compliance | v5T (No fine pages) |
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|FCSE Support | Yes |
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|FCSE Support | Yes |
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* 10-stage pipeline design. Pipeline has bypass network to resolve dependencies. Most operations execute at a rate of 1 operation per clock.
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* 10-stage pipeline design. Pipeline has extensive bypass network to resolve dependencies. Most operations execute at a rate of 1 operation per clock.
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* 2 write ports for the register file to allow LDR/STR with writeback to execute as a single instruction.
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* 2 write ports for the register file to allow LDR/STR with writeback to execute as a single instruction.
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* Instructions of ALU + Shift can allow execution of subsequent commands with dependencies if the subsequent command doesn't use the shifter. This is done by having a dual feedback network.
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* The core is specifically designed for use in FGPA and relies on FGPA inference to allow portability across FPGA vendors.
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#### CPU Configuration (zap_top.v)
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#### CPU Configuration (zap_top.v)
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| Parameter | Default| Description |
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| Parameter | Default| Description |
|
|--------------------------|--------|-------------|
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|--------------------------|--------|-------------|
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| Line 88... |
Line 92... |
| output | | o_wb_stb_nxt | IGNORE THIS PORT. LEAVE OPEN. |
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| output | | o_wb_stb_nxt | IGNORE THIS PORT. LEAVE OPEN. |
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| output | | o_wb_cyc_nxt | IGNORE THIS PORT. LEAVE OPEN. |
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| output | | o_wb_cyc_nxt | IGNORE THIS PORT. LEAVE OPEN. |
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| output | [31:0] | o_wb_adr_nxt | IGNORE THIS PORT. LEAVE OPEN. |
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| output | [31:0] | o_wb_adr_nxt | IGNORE THIS PORT. LEAVE OPEN. |
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### Getting Started
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### Run Sample Tests
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*Tested on Ubuntu 16.04 LTS/18.04 LTS*
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|
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#### Run Sample Tests
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*Tested on Ubuntu 16.04 LTS/18.04 LTS*
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Let the variable $test_name hold the name of the test. See the src/ts directory for some basic tests pre-installed. Available test names are: factorial, arm_test, thumb_test, uart. New tests can be added using these as starting templates. Please note that these will be run on the SOC platform (chip_top) that consist of the ZAP processor, 2 x UARTs, a VIC and a timer.
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Let the variable $test_name hold the name of the test. See the src/ts directory for some basic tests pre-installed. Available test names are: factorial, arm_test, thumb_test, uart. New tests can be added using these as starting templates. Please note that these will be run on the SOC platform (chip_top) that consist of the ZAP processor, 2 x UARTs, a VIC and a timer.
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|
```bash
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```bash
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sudo apt-get install sudo apt-get install gcc-arm-none-eabi binutils-arm-none-eabi gdb openocd iverilog gtkwave make perl xterm
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sudo apt-get install sudo apt-get install gcc-arm-none-eabi binutils-arm-none-eabi gdb openocd iverilog gtkwave make perl xterm
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| Line 105... |
Line 108... |
gvim zap.log.gz # View the log file
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gvim zap.log.gz # View the log file
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gtkwave zap.vcd.gz # Exists if selected by Config.cfg. See PDF document for more information.
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gtkwave zap.vcd.gz # Exists if selected by Config.cfg. See PDF document for more information.
|
```
|
```
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To use this processor in your SOC, instantiate this top level CPU module in your project: /src/rtl/cpu/zap_top.v
|
To use this processor in your SOC, instantiate this top level CPU module in your project: /src/rtl/cpu/zap_top.v
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### Implementation Specific Details
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### FPGA Timing Performance (Vivado, Retime Enabled)
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|
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#### FPGA Timing Performance (Vivado, Retime Enabled)
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| FPGA Part | Speed | Critical Path |
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| FPGA Part | Speed | Critical Path |
|
|--------------------|-------|----------------|
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|--------------------|-------|----------------|
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| xc7a35tiftg256-1L | 80MHz | Cache access |
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| xc7a35tiftg256-1L | 80MHz | Cache access |
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|
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#### Coprocessor #15 Control Registers
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|
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##### Register 0 : ID Register
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|
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|Bits | Name | Description |
|
|
|-----|---------|------------------------------------------|
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|31:0 | Various | Processor ID info. |
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##### Register 1 : Control
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|
|
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|Bits | Name | Description |
|
|
|-----|-----------|------------------------------------------|
|
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|0 | M | MMU Enable. Active high |
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|1 | A | Always 0. Alignment check off |
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|2 | D | Data Cache Enable. Active high |
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|3 | W | Always 1. Write Buffer always on. |
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|4 | P | Always 1. RESERVED |
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|5 | D | Always 1. RESERVED |
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|6 | L | Always 1. RESERVED |
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|7 | B | Always 0. Little Endian |
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|8 | S | The S bit |
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|9 | R | The R bit |
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|11 | Z | Always 1. Branch prediction enabled |
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|12 | I | Instruction Cache Enable. Active high |
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|13 | V | Normal Exception Vectors. Always 0 |
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|14 | RR | Always 1. Direct mapped cache. |
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|15 | L4 | Always 0. Normal behavior. |
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##### Register 2 : Translation Base Address
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|
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|Bits | Name | Description |
|
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|-----|-----------|------------------------------------------|
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|13:0 | M | Preserve value. |
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|31:14| TTB | Upper 18-bits of translation address |
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|
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##### Register 3 : Domain Access Control (X=0 to X=15)
|
|
|
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|Bits | Name | Description |
|
|
|---------|-----------|------------------------------------------|
|
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|2X+1:2X | DX | DX access permission. |
|
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|
|
##### Register 5 : Fault Status Register
|
|
|
|
|Bits | Name | Description |
|
|
|-----|-----------|------------------------------------------|
|
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|3:0 | Status | Status. |
|
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|1:0 | Domain | Domain. |
|
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|11:8 | SBZ | Always 0. RESERVED |
|
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|
|
##### Register 6 : Fault Address Register
|
|
|
|
|Bits | Name | Description |
|
|
|-----|-----------|------------------------------------------|
|
|
|31:0 | Addr | Fault Address. |
|
|
|
|
##### Register 7 : Cache Functions
|
|
|
|
| Opcode2 | CRm | Description |
|
|
|-------------|-----------------|-------------------------------------|
|
|
| 000 | 0111 | Flush all caches. |
|
|
| 000 | 0101 | Flush I cache. |
|
|
| 000 | 0110 | Flush D cache. |
|
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| 000 | 1011 | Clean all caches. |
|
|
| 000 | 1010 | Clean D cache. |
|
|
| 000 | 1111 | Clean and flush all caches. |
|
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| 000 | 1110 | Clean and flush D cache. |
|
|
| Other | Other | Clean and flush ALL caches |
|
|
|
|
|
|
##### Register 8 : TLB Functions
|
|
|
|
|Opcode2 | CRm | Description |
|
|
|--------|---------------|-------------------------|
|
|
| 000 | 0111 | Flush all TLBs |
|
|
| 000 | 0101 | Flush I TLB |
|
|
| 000 | 0110 | Flush D TLB |
|
|
| Other| Other | Flush all TLBs |
|
|
|
|
##### Register 13 : FCSE Extentions
|
|
|
|
| Field | Description |
|
|
|-------|-------------|
|
|
| 31:25 | PID |
|
|
|
|
##### Lockdown Support
|
|
* CPU memory system does not support lockdown.
|
|
|
|
##### Tiny Pages
|
|
* No support for tiny pages (1KB).
|
|
|
|
### License
|
### License
|
|
|
|
|
GNU GENERAL PUBLIC LICENSE
|
GNU GENERAL PUBLIC LICENSE
|
Version 2, June 1991
|
Version 2, June 1991
|
