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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_alu_main.v] - Diff between revs 26 and 37

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Rev 26 Rev 37
Line 264... Line 264...
reg [31:0]                      rm, rn; // RM = shifted source value Rn for
reg [31:0]                      rm, rn; // RM = shifted source value Rn for
                                        // non shifted source value. These are
                                        // non shifted source value. These are
                                        // values and not indices.
                                        // values and not indices.
 
 
 
 
 
reg [5:0]                       clz_rm; // Count leading zeros in Rm.
 
 
 
always @* // CLZ implementation.
 
begin
 
        casez(rm)
 
        32'b1???????????????????????????????:   clz_rm = 6'd00;
 
        32'b01??????????????????????????????:   clz_rm = 6'd01;
 
        32'b001?????????????????????????????:   clz_rm = 6'd02;
 
        32'b0001????????????????????????????:   clz_rm = 6'd03;
 
        32'b00001???????????????????????????:   clz_rm = 6'd04;
 
        32'b000001??????????????????????????:   clz_rm = 6'd05;
 
        32'b0000001?????????????????????????:   clz_rm = 6'd06;
 
        32'b00000001????????????????????????:   clz_rm = 6'd07;
 
        32'b000000001???????????????????????:   clz_rm = 6'd08;
 
        32'b0000000001??????????????????????:   clz_rm = 6'd09;
 
        32'b00000000001?????????????????????:   clz_rm = 6'd10;
 
        32'b000000000001????????????????????:   clz_rm = 6'd11;
 
        32'b0000000000001???????????????????:   clz_rm = 6'd12;
 
        32'b00000000000001??????????????????:   clz_rm = 6'd13;
 
        32'b000000000000001?????????????????:   clz_rm = 6'd14;
 
        32'b0000000000000001????????????????:   clz_rm = 6'd15;
 
        32'b00000000000000001???????????????:   clz_rm = 6'd16;
 
        32'b000000000000000001??????????????:   clz_rm = 6'd17;
 
        32'b0000000000000000001?????????????:   clz_rm = 6'd18;
 
        32'b00000000000000000001????????????:   clz_rm = 6'd19;
 
        32'b000000000000000000001???????????:   clz_rm = 6'd20;
 
        32'b0000000000000000000001??????????:   clz_rm = 6'd21;
 
        32'b00000000000000000000001?????????:   clz_rm = 6'd22;
 
        32'b000000000000000000000001????????:   clz_rm = 6'd23;
 
        32'b0000000000000000000000001???????:   clz_rm = 6'd24;
 
        32'b00000000000000000000000001??????:   clz_rm = 6'd25;
 
        32'b000000000000000000000000001?????:   clz_rm = 6'd26;
 
        32'b0000000000000000000000000001????:   clz_rm = 6'd27;
 
        32'b00000000000000000000000000001???:   clz_rm = 6'd28;
 
        32'b000000000000000000000000000001??:   clz_rm = 6'd29;
 
        32'b0000000000000000000000000000001?:   clz_rm = 6'd30;
 
        32'b00000000000000000000000000000001:   clz_rm = 6'd31;
 
        default:                                clz_rm = 6'd32; // All zeros.
 
        endcase
 
end
 
 
// Destination index about to be output.
// Destination index about to be output.
reg [zap_clog2(PHY_REGS)-1:0]      o_destination_index_nxt;
reg [zap_clog2(PHY_REGS)-1:0]      o_destination_index_nxt;
 
 
// 1s complement of Rm and Rn.
// 1s complement of Rm and Rn.
Line 573... Line 613...
                //
                //
                if ( i_flag_update_ff )
                if ( i_flag_update_ff )
                        tmp_flags[31:28] = {n,z,c,v};
                        tmp_flags[31:28] = {n,z,c,v};
 
 
                // Write out the result.
                // Write out the result.
                tmp_sum = sum;
                tmp_sum = op == CLZ ? clz_rm : sum;
        end
        end
 
 
        // Drive nxt pin of result register.
        // Drive nxt pin of result register.
        o_alu_result_nxt = tmp_sum;
        o_alu_result_nxt = tmp_sum;
end
end

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