OpenCores
URL https://opencores.org/ocsvn/zap/zap/trunk

Subversion Repositories zap

[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_cache.v] - Diff between revs 26 and 43

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 26 Rev 43
Line 85... Line 85...
 
 
`include "zap_defines.vh"
`include "zap_defines.vh"
`include "zap_localparams.vh"
`include "zap_localparams.vh"
`include "zap_functions.vh"
`include "zap_functions.vh"
 
 
 
localparam                      S0=0;
 
localparam                      S1=1;
 
localparam                      S2=2;
 
 
wire [2:0]       wb_stb;
wire [2:0]       wb_stb;
wire [2:0]       wb_cyc;
wire [2:0]       wb_cyc;
wire [2:0]       wb_wen;
wire [2:0]       wb_wen;
wire [3:0]       wb_sel [2:0];
wire [3:0]       wb_sel [2:0];
wire [31:0]      wb_dat [2:0];
wire [31:0]      wb_dat [2:0];
wire [31:0]      wb_adr [2:0];
wire [31:0]      wb_adr [2:0];
wire [2:0]       wb_cti [2:0];
wire [2:0]       wb_cti [2:0];
 
 
assign wb_cti[2] = 0;
 
 
 
wire [31:0] wb_dat0_cachefsm, wb_dat1_tagram, wb_dat2_tlb;
wire [31:0] wb_dat0_cachefsm, wb_dat1_tagram, wb_dat2_tlb;
wire [31:0] unused_dat = wb_dat0_cachefsm | wb_dat1_tagram | wb_dat2_tlb;
 
assign wb_dat0_cachefsm = wb_dat[0];
 
assign wb_dat1_tagram = wb_dat[1];
 
assign wb_dat2_tlb = wb_dat[2];
 
 
 
wire [31:0] tlb_phy_addr;
wire [31:0] tlb_phy_addr;
wire [7:0] tlb_fsr;
wire [7:0] tlb_fsr;
wire [31:0] tlb_far;
wire [31:0] tlb_far;
wire tlb_fault;
wire tlb_fault;
wire tlb_cacheable;
wire tlb_cacheable;
wire tlb_busy;
wire tlb_busy;
 
 
wire [127:0] tr_cache_line;
wire [127:0] tr_cache_line;
wire [127:0] cf_cache_line;
wire [127:0] cf_cache_line;
wire [15:0] cf_cache_line_ben;
wire [15:0] cf_cache_line_ben;
wire cf_cache_tag_wr_en;
wire cf_cache_tag_wr_en;
 
 
wire [`CACHE_TAG_WDT-1:0] tr_cache_tag, cf_cache_tag;
wire [`CACHE_TAG_WDT-1:0] tr_cache_tag, cf_cache_tag;
wire tr_cache_tag_valid;
wire tr_cache_tag_valid;
wire tr_cache_tag_dirty, cf_cache_tag_dirty;
wire tr_cache_tag_dirty, cf_cache_tag_dirty;
 
 
wire cf_cache_clean_req, cf_cache_inv_req;
wire cf_cache_clean_req, cf_cache_inv_req;
 
 
wire tr_cache_inv_done, tr_cache_clean_done;
wire tr_cache_inv_done, tr_cache_clean_done;
 
reg [2:0]                       wb_ack;
 
reg [1:0]                       state_ff, state_nxt;
 
 
 
// Data from each Wishbone master.
 
assign wb_dat0_cachefsm = wb_dat[0];
 
assign wb_dat1_tagram   = wb_dat[1];
 
assign wb_dat2_tlb      = wb_dat[2];
 
 
zap_cache_fsm #(.CACHE_SIZE(CACHE_SIZE))
// Bit 2 of Wishbone CTI is always on all CPU supported modes.
u_zap_cache_fsm         (
assign wb_cti[2] = 0;
 
 
 
// Basic cache FSM - serves as Master 0.
 
zap_cache_fsm #(.CACHE_SIZE(CACHE_SIZE)) u_zap_cache_fsm (
.i_clk                  (i_clk),
.i_clk                  (i_clk),
.i_reset                (i_reset),
.i_reset                (i_reset),
.i_address              (i_address),
.i_address              (i_address),
.i_rd                   (i_rd),
.i_rd                   (i_rd),
.i_wr                   (i_wr),
.i_wr                   (i_wr),
Line 140... Line 142...
.i_cache_en             (i_cache_en),
.i_cache_en             (i_cache_en),
.i_cache_inv            (i_cache_inv_req),
.i_cache_inv            (i_cache_inv_req),
.i_cache_clean          (i_cache_clean_req),
.i_cache_clean          (i_cache_clean_req),
.o_cache_inv_done       (o_cache_inv_done),
.o_cache_inv_done       (o_cache_inv_done),
.o_cache_clean_done     (o_cache_clean_done),
.o_cache_clean_done     (o_cache_clean_done),
 
 
.i_cache_line           (tr_cache_line),
.i_cache_line           (tr_cache_line),
 
 
.i_cache_tag_dirty      (tr_cache_tag_dirty),
.i_cache_tag_dirty      (tr_cache_tag_dirty),
.i_cache_tag            (tr_cache_tag),
.i_cache_tag            (tr_cache_tag),
.i_cache_tag_valid      (tr_cache_tag_valid),
.i_cache_tag_valid      (tr_cache_tag_valid),
.o_cache_tag            (cf_cache_tag),
.o_cache_tag            (cf_cache_tag),
.o_cache_tag_dirty      (cf_cache_tag_dirty),
.o_cache_tag_dirty      (cf_cache_tag_dirty),
.o_cache_tag_wr_en      (cf_cache_tag_wr_en),
.o_cache_tag_wr_en      (cf_cache_tag_wr_en),
.o_cache_line           (cf_cache_line),
.o_cache_line           (cf_cache_line),
.o_cache_line_ben       (cf_cache_line_ben),
.o_cache_line_ben       (cf_cache_line_ben),
 
 
.o_cache_clean_req      (cf_cache_clean_req),
.o_cache_clean_req      (cf_cache_clean_req),
.i_cache_clean_done     (tr_cache_clean_done),
.i_cache_clean_done     (tr_cache_clean_done),
.o_cache_inv_req        (cf_cache_inv_req),
.o_cache_inv_req        (cf_cache_inv_req),
.i_cache_inv_done       (tr_cache_inv_done),
.i_cache_inv_done       (tr_cache_inv_done),
 
 
.i_phy_addr             (tlb_phy_addr),
.i_phy_addr             (tlb_phy_addr),
.i_fsr                  (tlb_fsr),
.i_fsr                  (tlb_fsr),
.i_far                  (tlb_far),
.i_far                  (tlb_far),
.i_fault                (tlb_fault),
.i_fault                (tlb_fault),
.i_cacheable            (tlb_cacheable),
.i_cacheable            (tlb_cacheable),
.i_busy                 (tlb_busy),
.i_busy                 (tlb_busy),
 
 
.o_wb_cyc_ff            (),
.o_wb_cyc_ff            (),
.o_wb_cyc_nxt           (wb_cyc[0]),
.o_wb_cyc_nxt           (wb_cyc[0]),
.o_wb_stb_ff            (),
.o_wb_stb_ff            (),
.o_wb_stb_nxt           (wb_stb[0]),
.o_wb_stb_nxt           (wb_stb[0]),
.o_wb_adr_ff            (),
.o_wb_adr_ff            (),
Line 182... Line 179...
.o_wb_cti_nxt           (wb_cti[0]),
.o_wb_cti_nxt           (wb_cti[0]),
.i_wb_dat               (i_wb_dat),
.i_wb_dat               (i_wb_dat),
.i_wb_ack               (wb_ack[0])
.i_wb_ack               (wb_ack[0])
);
);
 
 
zap_cache_tag_ram #(.CACHE_SIZE(CACHE_SIZE))
// Cache Tag RAM - As a master - this performs cache clean - Master 1.
u_zap_cache_tag_ram     (
zap_cache_tag_ram #(.CACHE_SIZE(CACHE_SIZE)) u_zap_cache_tag_ram     (
 
 
.i_clk                  (i_clk),
.i_clk                  (i_clk),
.i_reset                (i_reset),
.i_reset                (i_reset),
.i_address_nxt          (i_address_nxt),
.i_address_nxt          (i_address_nxt),
.i_address              (i_address),
.i_address              (i_address),
 
 
.i_cache_en             (i_cache_en),
.i_cache_en             (i_cache_en),
 
 
.i_cache_line           (cf_cache_line),
.i_cache_line           (cf_cache_line),
.o_cache_line           (tr_cache_line),
.o_cache_line           (tr_cache_line),
 
 
.i_cache_line_ben       (cf_cache_line_ben),
.i_cache_line_ben       (cf_cache_line_ben),
.i_cache_tag_wr_en      (cf_cache_tag_wr_en),
.i_cache_tag_wr_en      (cf_cache_tag_wr_en),
 
 
.i_cache_tag            (cf_cache_tag),
.i_cache_tag            (cf_cache_tag),
.i_cache_tag_dirty      (cf_cache_tag_dirty),
.i_cache_tag_dirty      (cf_cache_tag_dirty),
 
 
.o_cache_tag            (tr_cache_tag),
.o_cache_tag            (tr_cache_tag),
.o_cache_tag_valid      (tr_cache_tag_valid),
.o_cache_tag_valid      (tr_cache_tag_valid),
.o_cache_tag_dirty      (tr_cache_tag_dirty),
.o_cache_tag_dirty      (tr_cache_tag_dirty),
 
 
.i_cache_inv_req        (cf_cache_inv_req),
.i_cache_inv_req        (cf_cache_inv_req),
.o_cache_inv_done       (tr_cache_inv_done),
.o_cache_inv_done       (tr_cache_inv_done),
.i_cache_clean_req      (cf_cache_clean_req),
.i_cache_clean_req      (cf_cache_clean_req),
.o_cache_clean_done     (tr_cache_clean_done),
.o_cache_clean_done     (tr_cache_clean_done),
 
 
// Cache clean operations occur through these ports.
 
.o_wb_cyc_ff            (),
.o_wb_cyc_ff            (),
.o_wb_cyc_nxt           (wb_cyc[1]),
.o_wb_cyc_nxt           (wb_cyc[1]),
.o_wb_stb_ff            (),
.o_wb_stb_ff            (),
.o_wb_stb_nxt           (wb_stb[1]),
.o_wb_stb_nxt           (wb_stb[1]),
.o_wb_adr_ff            (),
.o_wb_adr_ff            (),
Line 229... Line 217...
.o_wb_cti_nxt           (wb_cti[1]),
.o_wb_cti_nxt           (wb_cti[1]),
.i_wb_dat               (i_wb_dat),
.i_wb_dat               (i_wb_dat),
.i_wb_ack               (wb_ack[1])
.i_wb_ack               (wb_ack[1])
);
);
 
 
 
// ZAP TLB control module. Includes TLB RAM inside.
zap_tlb #(
zap_tlb #(
.LPAGE_TLB_ENTRIES      (LPAGE_TLB_ENTRIES),
.LPAGE_TLB_ENTRIES      (LPAGE_TLB_ENTRIES),
.SPAGE_TLB_ENTRIES      (SPAGE_TLB_ENTRIES),
.SPAGE_TLB_ENTRIES      (SPAGE_TLB_ENTRIES),
.SECTION_TLB_ENTRIES    (SECTION_TLB_ENTRIES))
.SECTION_TLB_ENTRIES    (SECTION_TLB_ENTRIES))
u_zap_tlb (
u_zap_tlb (
Line 246... Line 235...
.i_sr           (i_sr),
.i_sr           (i_sr),
.i_dac_reg      (i_dac_reg),
.i_dac_reg      (i_dac_reg),
.i_baddr        (i_baddr),
.i_baddr        (i_baddr),
.i_mmu_en       (i_mmu_en),
.i_mmu_en       (i_mmu_en),
.i_inv          (i_tlb_inv),
.i_inv          (i_tlb_inv),
 
 
.o_phy_addr     (tlb_phy_addr),
.o_phy_addr     (tlb_phy_addr),
.o_fsr          (tlb_fsr),
.o_fsr          (tlb_fsr),
.o_far          (tlb_far),
.o_far          (tlb_far),
.o_fault        (tlb_fault),
.o_fault        (tlb_fault),
.o_cacheable    (tlb_cacheable),
.o_cacheable    (tlb_cacheable),
.o_busy         (tlb_busy),
.o_busy         (tlb_busy),
 
 
.o_wb_stb_nxt   (wb_stb[2]),
.o_wb_stb_nxt   (wb_stb[2]),
.o_wb_cyc_nxt   (wb_cyc[2]),
.o_wb_cyc_nxt   (wb_cyc[2]),
.o_wb_adr_nxt   (wb_adr[2]),
.o_wb_adr_nxt   (wb_adr[2]),
.o_wb_wen_nxt   (wb_wen[2]),
.o_wb_wen_nxt   (wb_wen[2]),
.o_wb_sel_nxt   (wb_sel[2]),
.o_wb_sel_nxt   (wb_sel[2]),
.o_wb_dat_nxt   (wb_dat[2]),
.o_wb_dat_nxt   (wb_dat[2]),
.i_wb_dat       (i_wb_dat),
.i_wb_dat       (i_wb_dat),
.i_wb_ack       (wb_ack[2])
.i_wb_ack       (wb_ack[2])
);
);
 
 
localparam S0=0;
// Sequential Block
localparam S1=1;
 
localparam S2=2;
 
 
 
reg [2:0] wb_ack;
 
reg [1:0] state_ff, state_nxt;
 
 
 
always @ (posedge i_clk)
always @ (posedge i_clk)
begin
begin
        if ( i_reset )
        if ( i_reset )
        begin
        begin
                state_ff <= S0;
                state_ff <= S0;
Line 297... Line 278...
                o_wb_dat <= o_wb_dat_nxt;
                o_wb_dat <= o_wb_dat_nxt;
                o_wb_wen <= o_wb_wen_nxt;
                o_wb_wen <= o_wb_wen_nxt;
        end
        end
end
end
 
 
 
// Next state logic.
always @*
always @*
begin
begin
        state_nxt = state_ff;
        state_nxt = state_ff;
 
 
        // Change state only if strobe is inactive or strobe has just completed.
        // Change state only if strobe is inactive or strobe has just completed.
Line 313... Line 295...
                default: state_nxt = state_ff;
                default: state_nxt = state_ff;
                endcase
                endcase
        end
        end
end
end
 
 
 
// Route ACKs to respective masters.
always @*
always @*
begin
begin
        wb_ack = 0;
        wb_ack = 0;
 
 
        case(state_ff)
        case(state_ff)
Line 336... Line 319...
        o_wb_cti_nxt = wb_cti[state_nxt];
        o_wb_cti_nxt = wb_cti[state_nxt];
        o_wb_sel_nxt = wb_sel[state_nxt];
        o_wb_sel_nxt = wb_sel[state_nxt];
        o_wb_wen_nxt = wb_wen[state_nxt];
        o_wb_wen_nxt = wb_wen[state_nxt];
end
end
 
 
// synopsys translate_off
// assertions_start
reg xerr;
        reg     xerr = 0;
initial xerr = 0;
 
 
 
always @ (posedge i_clk)
always @ (posedge i_clk)
begin // Check if data delivered to processor is x.
        begin
 
                // Check if data delivered to processor is 'x'.
        if ( o_dat[0] === 1'dx && o_ack && i_rd )
        if ( o_dat[0] === 1'dx && o_ack && i_rd )
        begin
        begin
                $display($time, "Error : %m Data went to x when giving data to core...");
                        $display($time, "Error : %m Data went to x when giving data to core.");
                xerr = xerr + 1;
                xerr = xerr + 1;
                $stop;
                $stop;
        end
        end
end
end
// synopsys translate_on
// assertions_end
 
 
 
endmodule // zap_cache
 
 
endmodule
 
`default_nettype wire
`default_nettype wire
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.