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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_cache_fsm.v] - Diff between revs 29 and 43

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Line 31... Line 31...
 
 
`include "zap_defines.vh"
`include "zap_defines.vh"
 
 
module zap_cache_fsm   #(
module zap_cache_fsm   #(
parameter CACHE_SIZE    = 1024  // Bytes.
parameter CACHE_SIZE    = 1024  // Bytes.
) /* Port List */       (
)
 
 
 
// ---------------------------------------------- 
 
//  Port List 
 
// ----------------------------------------------        
 
 
 
(
 
 
/* Clock and reset */
/* Clock and reset */
input   wire                      i_clk,
input   wire                      i_clk,
input   wire                      i_reset,
input   wire                      i_reset,
 
 
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input   wire            i_wb_ack,
input   wire            i_wb_ack,
input   wire    [31:0]  i_wb_dat
input   wire    [31:0]  i_wb_dat
 
 
);
);
 
 
 
// -------------------------------------------------------------
 
// Includes and Localparams
 
// -------------------------------------------------------------
 
 
`include "zap_localparams.vh"
`include "zap_localparams.vh"
`include "zap_defines.vh"
`include "zap_defines.vh"
`include "zap_functions.vh"
`include "zap_functions.vh"
 
 
/* Signal aliases */
 
wire cache_cmp   = (i_cache_tag[`CACHE_TAG__TAG] == i_address[`VA__CACHE_TAG]);
 
wire cache_dirty = i_cache_tag_dirty;
 
 
 
/* States */
/* States */
localparam IDLE                 = 0; /* Resting state. */
localparam IDLE                 = 0; /* Resting state. */
localparam UNCACHEABLE          = 1; /* Uncacheable access. */
localparam UNCACHEABLE          = 1; /* Uncacheable access. */
localparam REFRESH_1            = 2; /* Cache write hit state. Unused. */
localparam REFRESH_1            = 2; /* Cache write hit state. Unused. */
localparam CLEAN_SINGLE         = 3; /* Ultimately cleans up cache line. Parent state */
localparam CLEAN_SINGLE         = 3; /* Ultimately cleans up cache line. Parent state */
localparam FETCH_SINGLE         = 4; /* Ultimately validates cache line. Parent state */
localparam FETCH_SINGLE         = 4; /* Ultimately validates cache line. Parent state */
localparam REFRESH              = 5; /* Cache refresh parent state */
localparam REFRESH              = 5; /* Cache refresh parent state */
localparam INVALIDATE           = 6; /* Cache invalidate parent state */
localparam INVALIDATE           = 6; /* Cache invalidate parent state */
localparam CLEAN                = 7; /* Cache clean parent state */
localparam CLEAN                = 7; /* Cache clean parent state */
 
 
localparam NUMBER_OF_STATES     = 8;
localparam NUMBER_OF_STATES     = 8;
 
 
/* Flops */
// ---------------------------------------------------------------
 
// Signal aliases   
 
// ---------------------------------------------------------------
 
 
 
wire cache_cmp   = (i_cache_tag[`CACHE_TAG__TAG] == i_address[`VA__CACHE_TAG]);
 
wire cache_dirty = i_cache_tag_dirty;
 
 
 
// ---------------------------------------------------------------
 
// Variables
 
// ---------------------------------------------------------------
 
 
reg [$clog2(NUMBER_OF_STATES)-1:0] state_ff, state_nxt;
reg [$clog2(NUMBER_OF_STATES)-1:0] state_ff, state_nxt;
reg [31:0] buf_ff [3:0];
reg [31:0] buf_ff [3:0];
reg [31:0] buf_nxt[3:0];
reg [31:0] buf_nxt[3:0];
reg cache_clean_req_nxt, cache_clean_req_ff;
reg                                     cache_clean_req_nxt,
reg cache_inv_req_nxt, cache_inv_req_ff;
                                        cache_clean_req_ff;
 
reg                                     cache_inv_req_nxt,
/* Address Counter */
                                        cache_inv_req_ff;
reg [2:0] adr_ctr_ff, adr_ctr_nxt; // Needs to take on 0,1,2,3 AND 4(nxt).
reg [2:0] adr_ctr_ff, adr_ctr_nxt; // Needs to take on 0,1,2,3 AND 4(nxt).
 
reg                                     hit;                     // For debug only.
 
 
reg hit; // debug.
// ----------------------------------------------------------------
 
// Logic
 
// ----------------------------------------------------------------
 
 
 
/* Tie flops to the output */
always @* o_cache_clean_req = cache_clean_req_ff; // Tie req flop to output.
always @* o_cache_clean_req = cache_clean_req_ff; // Tie req flop to output.
always @* o_cache_inv_req = cache_inv_req_ff;
always @* o_cache_inv_req = cache_inv_req_ff;     // Tie inv flop to output.
 
 
 
/* Sequential Block */
always @ (posedge i_clk)
always @ (posedge i_clk)
begin
begin
        if ( i_reset )
        if ( i_reset )
        begin
        begin
                o_wb_cyc_ff <= 0;
                o_wb_cyc_ff <= 0;
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                buf_ff[2]               <= buf_nxt[2];
                buf_ff[2]               <= buf_nxt[2];
                buf_ff[3]               <= buf_nxt[3];
                buf_ff[3]               <= buf_nxt[3];
        end
        end
end
end
 
 
 
/* Combo block */
always @*
always @*
begin
begin
        /* Default values */
        /* Default values */
        state_nxt               = state_ff;
        state_nxt               = state_ff;
        adr_ctr_nxt             = adr_ctr_ff;
        adr_ctr_nxt             = adr_ctr_ff;
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        end
        end
 
 
        endcase
        endcase
end
end
 
 
 
// ------------------------------------------------------------------------
 
// Tasks and functions.
 
// ------------------------------------------------------------------------
 
 
function [31:0] adapt_cache_data
function [31:0] adapt_cache_data
(input [1:0] shift, input [127:0] cd);
(input [1:0] shift, input [127:0] cd);
begin: blk1
begin: blk1
        reg [31:0] shamt;
        reg [31:0] shamt;
        shamt = shift << 5;
        shamt = shift << 5;
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        shamt = sh << 5;
        shamt = sh << 5;
        clean_single_d = cl >> shamt; // Select specific 32-bit.
        clean_single_d = cl >> shamt; // Select specific 32-bit.
end
end
endfunction
endfunction
 
 
// ----------------------------------------------------------------------------
 
 
 
/* Function to generate Wishbone read signals. */
/* Function to generate Wishbone read signals. */
task  wb_prpr_read;
task  wb_prpr_read;
input [31:0] i_address;
input [31:0] i_address;
input [2:0]  i_cti;
input [2:0]  i_cti;
begin
begin
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        o_wb_cti_nxt = i_cti;
        o_wb_cti_nxt = i_cti;
        o_wb_dat_nxt = 0;
        o_wb_dat_nxt = 0;
end
end
endtask
endtask
 
 
// ----------------------------------------------------------------------------
 
 
 
/* Function to generate Wishbone write signals */
/* Function to generate Wishbone write signals */
task  wb_prpr_write;
task  wb_prpr_write;
input   [31:0]  i_data;
input   [31:0]  i_data;
input   [31:0]  i_address;
input   [31:0]  i_address;
input   [2:0]   i_cti;
input   [2:0]   i_cti;
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        o_wb_cti_nxt = i_cti;
        o_wb_cti_nxt = i_cti;
        o_wb_dat_nxt = i_data;
        o_wb_dat_nxt = i_data;
end
end
endtask
endtask
 
 
// ----------------------------------------------------------------------------
 
 
 
/* Disables Wishbone */
/* Disables Wishbone */
task  kill_access;
task  kill_access;
begin
begin
        o_wb_cyc_nxt = 0;
        o_wb_cyc_nxt = 0;
        o_wb_stb_nxt = 0;
        o_wb_stb_nxt = 0;
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endtask
endtask
 
 
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
// synopsys translate_off
// synopsys translate_off
 
 
wire [31:0] buf0_ff, buf1_ff, buf2_ff;
wire [31:0] buf0_ff, buf1_ff, buf2_ff;
 
 
assign buf0_ff = buf_ff[0];
assign buf0_ff = buf_ff[0];
assign buf1_ff = buf_ff[1];
assign buf1_ff = buf_ff[1];
assign buf2_ff = buf_ff[2];
assign buf2_ff = buf_ff[2];
 
 
wire [31:0] buf3_ff = buf_ff[3];
wire [31:0] buf3_ff = buf_ff[3];
wire [31:0] buf0_nxt = buf_nxt[0];
wire [31:0] buf0_nxt = buf_nxt[0];
wire [31:0] buf1_nxt = buf_nxt[1];
wire [31:0] buf1_nxt = buf_nxt[1];
wire [31:0] buf2_nxt = buf_nxt[2];
wire [31:0] buf2_nxt = buf_nxt[2];
wire [31:0] buf3_nxt = buf_nxt[3];
wire [31:0] buf3_nxt = buf_nxt[3];
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wire [31:0] dbg_ct_tag   = o_cache_tag[`CACHE_TAG__TAG];
wire [31:0] dbg_ct_tag   = o_cache_tag[`CACHE_TAG__TAG];
wire [31:0] dbg_ct_pa    = o_cache_tag[`CACHE_TAG__PA];
wire [31:0] dbg_ct_pa    = o_cache_tag[`CACHE_TAG__PA];
 
 
// synopsys translate_on
// synopsys translate_on
 
 
endmodule
endmodule // zap_cache_fsm
 
 
`default_nettype wire
`default_nettype wire
 
 
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