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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_cache_fsm.v] - Diff between revs 51 and 52

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Rev 51 Rev 52
Line 103... Line 103...
input   wire            i_wb_ack,
input   wire            i_wb_ack,
input   wire    [31:0]  i_wb_dat
input   wire    [31:0]  i_wb_dat
 
 
);
);
 
 
// -------------------------------------------------------------
// ----------------------------------------------------------------------------
// Includes and Localparams
// Includes and Localparams
// -------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
`include "zap_localparams.vh"
`include "zap_localparams.vh"
`include "zap_defines.vh"
`include "zap_defines.vh"
`include "zap_functions.vh"
`include "zap_functions.vh"
 
 
Line 259... Line 259...
 
 
                                2'b11: /* Cache hit */
                                2'b11: /* Cache hit */
                                begin
                                begin
                                        if ( i_rd ) /* Read request. */
                                        if ( i_rd ) /* Read request. */
                                        begin
                                        begin
                                                /* Accelerate performance */
                                                /*
 
                                                 * Accelerate performance
 
                                                 * Read throughput at 80MHz
 
                                                 * clock is 80M operations per
 
                                                 * second (Hit).
 
                                                 */
                                                o_dat   = adapt_cache_data(i_address[3:2], i_cache_line);
                                                o_dat   = adapt_cache_data(i_address[3:2], i_cache_line);
 
 
                                                hit = 1'd1;
                                                hit = 1'd1;
 
 
 
 
                                                o_ack   = 1'd1;
                                                o_ack   = 1'd1;
                                        end
                                        end
                                        else if ( i_wr ) /* Write request */
                                        else if ( i_wr ) /* Write request */
                                        begin
                                        begin
                                                state_nxt    = REFRESH_1;
                                                state_nxt    = REFRESH_1;
                                                o_ack        = 1'd0;
                                                o_ack        = 1'd0;
 
 
                                                /* Accelerate performance */
                                                /*
 
                                                 * Each write to cache takes
 
                                                 * 3 cycles. Write throuput at
 
                                                 * 80MHz is 26.6M operations per
 
                                                 * second (Hit).
 
                                                 */
                                                o_cache_line =
                                                o_cache_line =
                                                {i_din,i_din,i_din,i_din};
                                                {i_din,i_din,i_din,i_din};
 
 
                                                o_cache_line_ben  = ben_comp ( i_address[3:2], i_ben );
                                                o_cache_line_ben  = ben_comp ( i_address[3:2], i_ben );
 
 

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