OpenCores
URL https://opencores.org/ocsvn/zap/zap/trunk

Subversion Repositories zap

[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_core.v] - Diff between revs 26 and 43

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 26 Rev 43
Line 35... Line 35...
        // Depth of FIFO.
        // Depth of FIFO.
        parameter [31:0] FIFO_DEPTH = 4
        parameter [31:0] FIFO_DEPTH = 4
 )
 )
(
(
 
 
// Clock and reset.
// ------------------------------------------------
input wire                              i_clk,                  // ZAP clock.        
// Clock and reset. Reset is synchronous.
input wire                              i_reset,                // Active high synchronous reset.
// ------------------------------------------------
 
 
 
input wire                              i_clk,
 
input wire                              i_reset,
 
 
 
// -------------------------------------------------
// Wishbone memory access for data.
// Wishbone memory access for data.
 
// -------------------------------------------------
 
 
output wire                             o_data_wb_we,
output wire                             o_data_wb_we,
output wire                             o_data_wb_cyc,
output wire                             o_data_wb_cyc,
output wire                             o_data_wb_stb,
output wire                             o_data_wb_stb,
output wire[31:0]                       o_data_wb_adr,
output wire[31:0]                       o_data_wb_adr,
input wire                              i_data_wb_ack,
input wire                              i_data_wb_ack,
Line 61... Line 67...
output wire [31:0]                      o_data_wb_adr_nxt,
output wire [31:0]                      o_data_wb_adr_nxt,
 
 
// Force user view.
// Force user view.
output wire                             o_mem_translate,
output wire                             o_mem_translate,
 
 
 
// --------------------------------------------------
// Interrupts. Active high.
// Interrupts. Active high.
 
// --------------------------------------------------
 
 
input wire                              i_fiq,                  // FIQ signal.
input wire                              i_fiq,                  // FIQ signal.
input wire                              i_irq,                  // IRQ signal.
input wire                              i_irq,                  // IRQ signal.
 
 
 
// ---------------------------------------------------
// Wishbone instruction access ports.
// Wishbone instruction access ports.
 
// ---------------------------------------------------
 
 
output wire     [31:0]                  o_instr_wb_adr, // Code address.                  
output wire     [31:0]                  o_instr_wb_adr, // Code address.                  
output wire                             o_instr_wb_cyc, // Always 1.
output wire                             o_instr_wb_cyc, // Always 1.
output wire                             o_instr_wb_stb, // Always 1.
output wire                             o_instr_wb_stb, // Always 1.
output wire                             o_instr_wb_we,  // Always 0.
output wire                             o_instr_wb_we,  // Always 0.
input wire [31:0]                       i_instr_wb_dat, // A 32-bit ZAP instruction.
input wire [31:0]                       i_instr_wb_dat, // A 32-bit ZAP instruction.
Line 82... Line 94...
output wire                             o_instr_wb_stb_nxt,
output wire                             o_instr_wb_stb_nxt,
 
 
// Determines user or supervisory mode. Cache must use this for VM.
// Determines user or supervisory mode. Cache must use this for VM.
output wire      [31:0]                 o_cpsr,
output wire      [31:0]                 o_cpsr,
 
 
 
// -----------------------------------------------------
// For MMU/cache connectivity.
// For MMU/cache connectivity.
 
// -----------------------------------------------------
 
 
input wire      [31:0]                  i_fsr,
input wire      [31:0]                  i_fsr,
input wire      [31:0]                  i_far,
input wire      [31:0]                  i_far,
output wire      [31:0]                 o_dac,
output wire      [31:0]                 o_dac,
output wire      [31:0]                 o_baddr,
output wire      [31:0]                 o_baddr,
output wire                             o_mmu_en,
output wire                             o_mmu_en,
output wire      [1:0]                  o_sr,
output wire      [1:0]                  o_sr,
 
output wire                             o_pid,
output wire                             o_dcache_inv,
output wire                             o_dcache_inv,
output wire                             o_icache_inv,
output wire                             o_icache_inv,
output wire                             o_dcache_clean,
output wire                             o_dcache_clean,
output wire                             o_icache_clean,
output wire                             o_icache_clean,
output wire                             o_dtlb_inv,
output wire                             o_dtlb_inv,
Line 100... Line 116...
output wire                             o_dcache_en,
output wire                             o_dcache_en,
output wire                             o_icache_en,
output wire                             o_icache_en,
input   wire                            i_dcache_inv_done,
input   wire                            i_dcache_inv_done,
input   wire                            i_icache_inv_done,
input   wire                            i_icache_inv_done,
input   wire                            i_dcache_clean_done,
input   wire                            i_dcache_clean_done,
input   wire                            i_icache_clean_done,
input   wire                            i_icache_clean_done
 
 
// Pipeline stall and clear signals. Hi to lo priority order. Sent out of the
 
// core for use outside. These are generally not used.
 
//
 
output wire                             o_clear_from_writeback, // |   
 
output wire                             o_clear_from_alu,       // |
 
output wire                             o_stall_from_shifter,   // |
 
output wire                             o_stall_from_issue,     // |
 
output wire                             o_stall_from_decode,    // | Low Priority.
 
output wire                             o_clear_from_decode     // V
 
);
);
 
 
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
`include "zap_localparams.vh"
`include "zap_localparams.vh"
Line 137... Line 143...
wire      [$clog2(PHY_REGS)-1:0] copro_reg_wr_index;// Reg. file write index.
wire      [$clog2(PHY_REGS)-1:0] copro_reg_wr_index;// Reg. file write index.
wire      [$clog2(PHY_REGS)-1:0] copro_reg_rd_index;// Reg. file read index.
wire      [$clog2(PHY_REGS)-1:0] copro_reg_rd_index;// Reg. file read index.
wire      [31:0]                 copro_reg_wr_data; // Reg. file write data.
wire      [31:0]                 copro_reg_wr_data; // Reg. file write data.
wire     [31:0]                  copro_reg_rd_data; // Reg. file read data.
wire     [31:0]                  copro_reg_rd_data; // Reg. file read data.
 
 
wire reset; // From reset synchronizer.
wire                            reset;               // Tied to i_reset.
 
wire                            shelve;              // From writeback.
// From writeback.
wire                            fiq;                 // Tied to FIQ.
wire shelve;
wire                            irq;                 // Tied to IRQ.
 
 
// Interrupt synchronizer.
 
wire fiq;
 
wire irq;
 
 
 
// Clear and stall signals.
// Clear and stall signals.
wire stall_from_decode;
wire stall_from_decode;
wire clear_from_alu;
wire clear_from_alu;
wire stall_from_issue;
wire stall_from_issue;
wire clear_from_writeback;
wire clear_from_writeback;
 
wire                            data_stall;
 
wire                            code_stall;
 
wire                            instr_valid;
 
wire                            pipeline_is_not_empty;
 
 
// Fetch
// Fetch
wire [31:0] fetch_instruction;  // Instruction from the fetch unit.
wire [31:0] fetch_instruction;  // Instruction from the fetch unit.
wire        fetch_valid;        // Instruction valid from the fetch unit.
wire        fetch_valid;        // Instruction valid from the fetch unit.
wire        fetch_instr_abort;  // abort indicator.
wire        fetch_instr_abort;  // abort indicator.
Line 179... Line 185...
wire            predecode_val;
wire            predecode_val;
wire            predecode_force32;
wire            predecode_force32;
wire            predecode_und;
wire            predecode_und;
wire [1:0]      predecode_taken;
wire [1:0]      predecode_taken;
 
 
 
// Compressed decoder.
 
wire                            thumb_irq;
 
wire                            thumb_fiq;
 
wire                            thumb_iabort;
 
wire [34:0]                     thumb_instruction;
 
wire                            thumb_valid;
 
wire                            thumb_und;
 
wire                            thumb_force32;
 
wire [1:0]                      thumb_bp_state;
 
wire [31:0]                     thumb_pc_ff;
 
wire [31:0]                     thumb_pc_plus_8_ff;
 
 
// Decode
// Decode
wire [3:0]                      decode_condition_code;
wire [3:0]                      decode_condition_code;
wire [$clog2(PHY_REGS)-1:0]     decode_destination_index;
wire [$clog2(PHY_REGS)-1:0]     decode_destination_index;
wire [32:0]                     decode_alu_source_ff;
wire [32:0]                     decode_alu_source_ff;
wire [$clog2(ALU_OPS)-1:0]      decode_alu_operation_ff;
wire [$clog2(ALU_OPS)-1:0]      decode_alu_operation_ff;
Line 333... Line 351...
wire [31:0] rd_data_1;
wire [31:0] rd_data_1;
wire [31:0] rd_data_2;
wire [31:0] rd_data_2;
wire [31:0] rd_data_3;
wire [31:0] rd_data_3;
wire [31:0] cpsr_nxt, cpsr;
wire [31:0] cpsr_nxt, cpsr;
 
 
 
// Hijack interface - related to Writeback - ALU interaction.
wire        wb_hijack;
wire        wb_hijack;
wire [31:0] wb_hijack_op1;
wire [31:0] wb_hijack_op1;
wire [31:0] wb_hijack_op2;
wire [31:0] wb_hijack_op2;
wire        wb_hijack_cin;
wire        wb_hijack_cin;
wire [31:0] alu_hijack_sum;
wire [31:0] alu_hijack_sum;
 
 
 
// Decompile chain for debugging.
 
wire [64*8-1:0]                 decode_decompile;
 
wire [64*8-1:0]                 issue_decompile;
 
wire [64*8-1:0]                 shifter_decompile;
 
wire [64*8-1:0]                 alu_decompile;
 
wire [64*8-1:0]                 memory_decompile;
 
wire [64*8-1:0]                 rb_decompile;
 
 
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
assign o_cpsr        = alu_flags_ff;
assign o_cpsr        = alu_flags_ff;
 
 
// Pipeline controls exposed.
 
assign o_clear_from_writeback = clear_from_writeback;
 
assign o_clear_from_alu     = clear_from_alu;
 
assign o_stall_from_shifter = stall_from_shifter;
 
assign o_stall_from_issue   = stall_from_issue;
 
assign o_stall_from_decode  = stall_from_decode;
 
assign o_clear_from_decode  = clear_from_decode;
 
 
 
 
 
// Data wishbone signals (defaults).
 
assign o_data_wb_adr = {alu_address_ff[31:2], 2'd0};
assign o_data_wb_adr = {alu_address_ff[31:2], 2'd0};
assign o_data_wb_adr_nxt = {alu_address_nxt[31:2], 2'd0};
assign o_data_wb_adr_nxt = {alu_address_nxt[31:2], 2'd0};
 
 
// Default Wishbone values (Code). 
 
assign o_instr_wb_we  = 1'd0;
assign o_instr_wb_we  = 1'd0;
assign o_instr_wb_sel = 4'b1111;
assign o_instr_wb_sel = 4'b1111;
 
assign reset                    = i_reset;
// ----------------------------------------------------------------------------
assign irq                      = i_irq;
 
assign fiq                      = i_fiq;
assign reset    = i_reset; // Assume external synchronizer.
assign data_stall               = o_data_wb_stb && o_data_wb_cyc && !i_data_wb_ack;
assign irq      = i_irq;   // Assume externally synchronized to core clock.
assign code_stall               = (!o_instr_wb_stb && !o_instr_wb_cyc) || !i_instr_wb_ack;
assign fiq      = i_fiq;   // Assume externally synchronized to core clock.
assign instr_valid              = o_instr_wb_stb && o_instr_wb_cyc && i_instr_wb_ack & !shelve;
 
assign pipeline_is_not_empty    =         predecode_val                      ||
 
                                          (decode_condition_code    != NV)   ||
 
                                          (issue_condition_code_ff  != NV)   ||
 
                                          (shifter_condition_code_ff!= NV)   ||
 
                                          alu_dav_ff                         ||
 
                                          memory_dav_ff;
 
 
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
// =========================
// =========================
// FETCH STAGE 
// FETCH STAGE 
Line 380... Line 400...
u_zap_fetch_main (
u_zap_fetch_main (
        // Input.
        // Input.
        .i_clk                          (i_clk),
        .i_clk                          (i_clk),
        .i_reset                        (reset),
        .i_reset                        (reset),
 
 
        .i_code_stall                   ((!o_instr_wb_stb && !o_instr_wb_cyc) || !i_instr_wb_ack),
        .i_code_stall                   (code_stall),
 
 
        .i_clear_from_writeback         (clear_from_writeback),
        .i_clear_from_writeback         (clear_from_writeback),
        .i_clear_from_decode            (clear_from_decode),
        .i_clear_from_decode            (clear_from_decode),
 
 
        .i_data_stall                   (1'd0),
        .i_data_stall                   (1'd0),
Line 395... Line 415...
        .i_stall_from_issue             (1'd0),
        .i_stall_from_issue             (1'd0),
        .i_stall_from_decode            (1'd0),
        .i_stall_from_decode            (1'd0),
 
 
        .i_pc_ff                        (o_instr_wb_adr),
        .i_pc_ff                        (o_instr_wb_adr),
        .i_instruction                  (i_instr_wb_dat),
        .i_instruction                  (i_instr_wb_dat),
        .i_valid                        (o_instr_wb_stb && o_instr_wb_cyc && i_instr_wb_ack & !shelve),
        .i_valid                        (instr_valid),
        .i_instr_abort                  (i_instr_wb_err),
        .i_instr_abort                  (i_instr_wb_err),
 
 
        .i_cpsr_ff_t                    (alu_flags_ff[T]),
        .i_cpsr_ff_t                    (alu_flags_ff[T]),
 
 
        // Output.
        // Output.
Line 411... Line 431...
 
 
 
 
        .i_confirm_from_alu             (confirm_from_alu),
        .i_confirm_from_alu             (confirm_from_alu),
        .i_pc_from_alu                  (shifter_pc_ff),
        .i_pc_from_alu                  (shifter_pc_ff),
        .i_taken                        (shifter_taken_ff),
        .i_taken                        (shifter_taken_ff),
        .o_taken_ff                     (fetch_bp_state)
        .o_taken                        (fetch_bp_state)
);
);
 
 
// =========================
// =========================
// FIFO.
// FIFO.
// =========================
// =========================
Line 423... Line 443...
#( .WDT(67), .DEPTH(FIFO_DEPTH) ) U_ZAP_FIFO (
#( .WDT(67), .DEPTH(FIFO_DEPTH) ) U_ZAP_FIFO (
        .i_clk(i_clk),
        .i_clk(i_clk),
        .i_reset(i_reset),
        .i_reset(i_reset),
        .i_clear_from_writeback(clear_from_writeback),
        .i_clear_from_writeback(clear_from_writeback),
 
 
        .i_write_inhibit                ( (!o_instr_wb_stb && !o_instr_wb_cyc) || !i_instr_wb_ack ),
        .i_write_inhibit                ( code_stall ),
 
        .i_data_stall                   ( data_stall ),
        .i_data_stall(
 
                                        o_data_wb_stb &&
 
                                         o_data_wb_cyc &&
 
                                        !i_data_wb_ack
 
        ),
 
 
 
        .i_clear_from_alu(clear_from_alu),
        .i_clear_from_alu(clear_from_alu),
        .i_stall_from_shifter(stall_from_shifter),
        .i_stall_from_shifter(stall_from_shifter),
        .i_stall_from_issue(stall_from_issue),
        .i_stall_from_issue(stall_from_issue),
        .i_stall_from_decode(stall_from_decode),
        .i_stall_from_decode(stall_from_decode),
        .i_clear_from_decode(clear_from_decode),
        .i_clear_from_decode(clear_from_decode),
 
 
        .i_instr({fetch_pc_plus_8_ff, fetch_instr_abort, fetch_instruction, fetch_bp_state}),
        .i_instr({fetch_pc_plus_8_ff, fetch_instr_abort, fetch_instruction, fetch_bp_state}),
        .i_valid(fetch_valid),
        .i_valid(fetch_valid),
 
 
        .o_instr({fifo_pc_plus_8, fifo_instr_abort, fifo_instruction, fifo_bp_state}),
        .o_instr({fifo_pc_plus_8, fifo_instr_abort, fifo_instruction, fifo_bp_state}),
        .o_valid(fifo_valid),
        .o_valid(fifo_valid),
 
 
        .o_wb_stb(o_instr_wb_stb),
        .o_wb_stb(o_instr_wb_stb),
        .o_wb_stb_nxt(o_instr_wb_stb_nxt),
        .o_wb_stb_nxt(o_instr_wb_stb_nxt),
        .o_wb_cyc(o_instr_wb_cyc)
        .o_wb_cyc(o_instr_wb_cyc)
);
);
 
 
wire thumb_irq;
 
wire thumb_fiq;
 
wire thumb_iabort;
 
wire [34:0] thumb_instruction;
 
wire thumb_valid;
 
wire thumb_und;
 
wire thumb_force32;
 
wire [1:0] thumb_bp_state;
 
wire [31:0] thumb_pc_ff;
 
wire [31:0] thumb_pc_plus_8_ff;
 
 
 
// =========================
// =========================
// COMPRESSED DECODER STAGE
// COMPRESSED DECODER STAGE
// =========================
// =========================
zap_thumb_decoder u_zap_thumb_decoder (
zap_thumb_decoder u_zap_thumb_decoder (
.i_clk          (i_clk),
.i_clk          (i_clk),
.i_reset        (i_reset),
.i_reset        (i_reset),
.i_clear_from_writeback(clear_from_writeback),
.i_clear_from_writeback(clear_from_writeback),
.i_data_stall   (
.i_data_stall                           (data_stall),
                                        o_data_wb_stb &&
 
                                        o_data_wb_cyc &&
 
                                        !i_data_wb_ack
 
),
 
.i_clear_from_alu(clear_from_alu),
.i_clear_from_alu(clear_from_alu),
.i_stall_from_shifter(stall_from_shifter),
.i_stall_from_shifter(stall_from_shifter),
.i_stall_from_issue(stall_from_issue),
.i_stall_from_issue(stall_from_issue),
.i_stall_from_decode(stall_from_decode),
.i_stall_from_decode(stall_from_decode),
.i_clear_from_decode(clear_from_decode),
.i_clear_from_decode(clear_from_decode),
Line 516... Line 515...
        // Input.
        // Input.
        .i_clk                          (i_clk),
        .i_clk                          (i_clk),
        .i_reset                        (reset),
        .i_reset                        (reset),
 
 
        .i_clear_from_writeback         (clear_from_writeback),
        .i_clear_from_writeback         (clear_from_writeback),
        .i_data_stall                   (o_data_wb_stb &&
        .i_data_stall                   (data_stall),
                                         o_data_wb_cyc &&
 
                                        !i_data_wb_ack),
 
        .i_clear_from_alu               (clear_from_alu),
        .i_clear_from_alu               (clear_from_alu),
        .i_stall_from_shifter           (stall_from_shifter),
        .i_stall_from_shifter           (stall_from_shifter),
        .i_stall_from_issue             (stall_from_issue),
        .i_stall_from_issue             (stall_from_issue),
 
 
        .i_irq                          (thumb_irq),
        .i_irq                          (thumb_irq),
Line 541... Line 538...
 
 
        .i_force32                      (thumb_force32),
        .i_force32                      (thumb_force32),
        .i_und                          (thumb_und),
        .i_und                          (thumb_und),
 
 
        .i_copro_done                   (copro_done),
        .i_copro_done                   (copro_done),
        .i_pipeline_dav                 (
        .i_pipeline_dav                 (pipeline_is_not_empty),
                                          predecode_val                      ||
 
                                          (decode_condition_code    != NV)   ||
 
                                          (issue_condition_code_ff  != NV)   ||
 
                                          (shifter_condition_code_ff!= NV)   ||
 
                                          alu_dav_ff                         ||
 
                                          memory_dav_ff
 
                                        ),
 
 
 
        // Output.
        // Output.
        .o_stall_from_decode            (stall_from_decode),
        .o_stall_from_decode            (stall_from_decode),
        .o_pc_plus_8_ff                 (predecode_pc_plus_8),
        .o_pc_plus_8_ff                 (predecode_pc_plus_8),
 
 
Line 574... Line 564...
        .o_instruction_valid_ff         (predecode_val),
        .o_instruction_valid_ff         (predecode_val),
 
 
        .o_taken_ff                     (predecode_taken)
        .o_taken_ff                     (predecode_taken)
);
);
 
 
wire [64*8-1:0] decode_decompile;
 
 
 
// =====================
// =====================
// DECODE STAGE 
// DECODE STAGE 
// =====================
// =====================
 
 
zap_decode_main #(
zap_decode_main #(
Line 594... Line 582...
        // Input.
        // Input.
        .i_clk                          (i_clk),
        .i_clk                          (i_clk),
        .i_reset                        (reset),
        .i_reset                        (reset),
 
 
        .i_clear_from_writeback         (clear_from_writeback),
        .i_clear_from_writeback         (clear_from_writeback),
        .i_data_stall                   (o_data_wb_cyc &&
        .i_data_stall                   (data_stall),
                                         o_data_wb_stb &&
 
                                        !i_data_wb_ack),
 
        .i_clear_from_alu               (clear_from_alu),
        .i_clear_from_alu               (clear_from_alu),
        .i_stall_from_shifter           (stall_from_shifter),
        .i_stall_from_shifter           (stall_from_shifter),
        .i_stall_from_issue             (stall_from_issue),
        .i_stall_from_issue             (stall_from_issue),
        .i_thumb_und                    (predecode_und),
        .i_thumb_und                    (predecode_und),
        .i_irq                          (predecode_irq),
        .i_irq                          (predecode_irq),
Line 650... Line 636...
 
 
// ==================
// ==================
// ISSUE 
// ISSUE 
// ==================
// ==================
 
 
wire [64*8-1:0] issue_decompile;
 
 
 
zap_issue_main #(
zap_issue_main #(
        .PHY_REGS(PHY_REGS),
        .PHY_REGS(PHY_REGS),
        .SHIFT_OPS(SHIFT_OPS),
        .SHIFT_OPS(SHIFT_OPS),
        .ALU_OPS(ALU_OPS)
        .ALU_OPS(ALU_OPS)
 
 
Line 677... Line 661...
        // Inputs
        // Inputs
        .i_clk                          (i_clk),
        .i_clk                          (i_clk),
        .i_reset                        (reset),
        .i_reset                        (reset),
        .i_clear_from_writeback         (clear_from_writeback),
        .i_clear_from_writeback         (clear_from_writeback),
        .i_stall_from_shifter           (stall_from_shifter),
        .i_stall_from_shifter           (stall_from_shifter),
        .i_data_stall                   (o_data_wb_cyc &&
        .i_data_stall                   (data_stall),
                                         o_data_wb_stb &&
 
                                        !i_data_wb_ack),
 
        .i_clear_from_alu               (clear_from_alu),
        .i_clear_from_alu               (clear_from_alu),
        .i_pc_plus_8_ff                 (decode_pc_plus_8_ff),
        .i_pc_plus_8_ff                 (decode_pc_plus_8_ff),
        .i_condition_code_ff            (decode_condition_code),
        .i_condition_code_ff            (decode_condition_code),
        .i_destination_index_ff         (decode_destination_index),
        .i_destination_index_ff         (decode_destination_index),
        .i_alu_source_ff                (decode_alu_source_ff),
        .i_alu_source_ff                (decode_alu_source_ff),
Line 777... Line 759...
 
 
// =======================
// =======================
// SHIFTER STAGE 
// SHIFTER STAGE 
// =======================
// =======================
 
 
wire [64*8-1:0] shifter_decompile;
 
 
 
zap_shifter_main #(
zap_shifter_main #(
        .PHY_REGS(PHY_REGS),
        .PHY_REGS(PHY_REGS),
        .ALU_OPS(ALU_OPS),
        .ALU_OPS(ALU_OPS),
        .SHIFT_OPS(SHIFT_OPS)
        .SHIFT_OPS(SHIFT_OPS)
)
)
Line 800... Line 780...
        .i_und_ff(issue_und_ff),
        .i_und_ff(issue_und_ff),
        .o_und_ff(shifter_und_ff),
        .o_und_ff(shifter_und_ff),
 
 
        .o_nozero_ff(shifter_nozero_ff),
        .o_nozero_ff(shifter_nozero_ff),
 
 
        // Inputs.
 
        .i_clk                          (i_clk),
        .i_clk                          (i_clk),
        .i_reset                        (reset),
        .i_reset                        (reset),
 
 
        .i_clear_from_writeback         (clear_from_writeback),
        .i_clear_from_writeback         (clear_from_writeback),
        .i_data_stall                   (o_data_wb_cyc &&
        .i_data_stall                   (data_stall),
                                         o_data_wb_stb &&
 
                                        !i_data_wb_ack),
 
        .i_clear_from_alu               (clear_from_alu),
        .i_clear_from_alu               (clear_from_alu),
        .i_condition_code_ff            (issue_condition_code_ff),
        .i_condition_code_ff            (issue_condition_code_ff),
        .i_destination_index_ff         (issue_destination_index_ff),
        .i_destination_index_ff         (issue_destination_index_ff),
        .i_alu_operation_ff             (issue_alu_operation_ff),
        .i_alu_operation_ff             (issue_alu_operation_ff),
        .i_shift_operation_ff           (issue_shift_operation_ff),
        .i_shift_operation_ff           (issue_shift_operation_ff),
Line 889... Line 867...
 
 
// ===============
// ===============
// ALU STAGE 
// ALU STAGE 
// ===============
// ===============
 
 
wire [64*8-1:0] alu_decompile;
 
 
 
zap_alu_main #(
zap_alu_main #(
        .PHY_REGS(PHY_REGS),
        .PHY_REGS(PHY_REGS),
        .SHIFT_OPS(SHIFT_OPS),
        .SHIFT_OPS(SHIFT_OPS),
        .ALU_OPS(ALU_OPS)
        .ALU_OPS(ALU_OPS)
)
)
Line 917... Line 893...
        .i_und_ff(shifter_und_ff),
        .i_und_ff(shifter_und_ff),
        .o_und_ff(alu_und_ff),
        .o_und_ff(alu_und_ff),
 
 
        .i_nozero_ff ( shifter_nozero_ff ),
        .i_nozero_ff ( shifter_nozero_ff ),
 
 
         .i_clk                          (i_clk),// & i_instr_wb_ack),
         .i_clk                          (i_clk),
         .i_reset                        (reset),
         .i_reset                        (reset),
         .i_clear_from_writeback         (clear_from_writeback),   // | High Pri
         .i_clear_from_writeback         (clear_from_writeback),
         .i_data_stall                   (o_data_wb_cyc &&
         .i_data_stall                   (data_stall),
                                          o_data_wb_stb &&
         .i_cpsr_nxt                     (cpsr_nxt),
                                          !i_data_wb_ack),         // V Low Pri
 
 
 
         .i_cpsr_nxt                     (cpsr_nxt), // FROM WB
 
         .i_flag_update_ff               (shifter_flag_update_ff),
         .i_flag_update_ff               (shifter_flag_update_ff),
         .i_switch_ff                    (shifter_switch_ff),
         .i_switch_ff                    (shifter_switch_ff),
 
 
         .i_force32align_ff              (shifter_force32_ff),
         .i_force32align_ff              (shifter_force32_ff),
 
 
Line 1012... Line 985...
 
 
// ====================
// ====================
// MEMORY 
// MEMORY 
// ====================
// ====================
 
 
wire [64*8-1:0] memory_decompile; // For debug. Goes to RB DC ip.
 
 
 
zap_memory_main #(
zap_memory_main #(
       .PHY_REGS(PHY_REGS)
       .PHY_REGS(PHY_REGS)
)
)
u_zap_memory_main
u_zap_memory_main
(
(
Line 1037... Line 1008...
        .i_ubyte_ff                     (alu_ubyte_ff),     // Unsigned byte.
        .i_ubyte_ff                     (alu_ubyte_ff),     // Unsigned byte.
        .i_shalf_ff                     (alu_shalf_ff),     // Signed half word.
        .i_shalf_ff                     (alu_shalf_ff),     // Signed half word.
        .i_uhalf_ff                     (alu_uhalf_ff),     // Unsigned half word.
        .i_uhalf_ff                     (alu_uhalf_ff),     // Unsigned half word.
 
 
        .i_clear_from_writeback         (clear_from_writeback),
        .i_clear_from_writeback         (clear_from_writeback),
        .i_data_stall                   (o_data_wb_cyc && o_data_wb_stb
        .i_data_stall                   (data_stall),
                                                       && !i_data_wb_ack),
 
        .i_alu_result_ff                (alu_alu_result_ff),
        .i_alu_result_ff                (alu_alu_result_ff),
        .i_flags_ff                     (alu_flags_ff),
        .i_flags_ff                     (alu_flags_ff),
 
 
        .i_mem_load_ff                  (alu_mem_load_ff),
        .i_mem_load_ff                  (alu_mem_load_ff),
 
 
Line 1087... Line 1057...
 
 
 
 
        .o_mem_rd_data                 (memory_mem_rd_data)
        .o_mem_rd_data                 (memory_mem_rd_data)
);
);
 
 
wire [64*8-1:0] rb_decompile;
 
 
 
// ==================
// ==================
// WRITEBACK 
// WRITEBACK 
// ==================
// ==================
 
 
zap_writeback #(
zap_writeback #(
Line 1108... Line 1076...
        .i_clk                  (i_clk), // ZAP clock.
        .i_clk                  (i_clk), // ZAP clock.
 
 
 
 
        .i_reset                (reset),           // ZAP reset.
        .i_reset                (reset),           // ZAP reset.
        .i_valid                (memory_dav_ff),
        .i_valid                (memory_dav_ff),
        .i_data_stall           (o_data_wb_cyc && o_data_wb_stb
        .i_data_stall           (data_stall),
                                               && !i_data_wb_ack),
 
        .i_clear_from_alu       (clear_from_alu),
        .i_clear_from_alu       (clear_from_alu),
        .i_pc_from_alu          (pc_from_alu),
        .i_pc_from_alu          (pc_from_alu),
        .i_stall_from_decode    (stall_from_decode),
        .i_stall_from_decode    (stall_from_decode),
        .i_stall_from_issue     (stall_from_issue),
        .i_stall_from_issue     (stall_from_issue),
        .i_stall_from_shifter   (stall_from_shifter),
        .i_stall_from_shifter   (stall_from_shifter),
Line 1121... Line 1088...
        .i_thumb                (alu_flags_ff[T]), // To indicate thumb state.
        .i_thumb                (alu_flags_ff[T]), // To indicate thumb state.
 
 
        .i_clear_from_decode    (clear_from_decode),
        .i_clear_from_decode    (clear_from_decode),
        .i_pc_from_decode       (pc_from_decode),
        .i_pc_from_decode       (pc_from_decode),
 
 
        .i_code_stall           ((!o_instr_wb_stb && !o_instr_wb_cyc) || (!i_instr_wb_ack)),
        .i_code_stall           (code_stall),
 
 
        // Used to valid writes on i_wr_index1.
        // Used to valid writes on i_wr_index1.
        .i_mem_load_ff          (memory_mem_load_ff),
        .i_mem_load_ff          (memory_mem_load_ff),
 
 
        .i_rd_index_0           (rd_index_0),
        .i_rd_index_0           (rd_index_0),
Line 1194... Line 1161...
        .i_far                  (i_far),
        .i_far                  (i_far),
        .o_dac                  (o_dac),
        .o_dac                  (o_dac),
        .o_baddr                (o_baddr),
        .o_baddr                (o_baddr),
        .o_mmu_en               (o_mmu_en),
        .o_mmu_en               (o_mmu_en),
        .o_sr                   (o_sr),
        .o_sr                   (o_sr),
 
        .o_pid                  (o_pid),
        .o_dcache_inv           (o_dcache_inv),
        .o_dcache_inv           (o_dcache_inv),
        .o_icache_inv           (o_icache_inv),
        .o_icache_inv           (o_icache_inv),
        .o_dcache_clean         (o_dcache_clean),
        .o_dcache_clean         (o_dcache_clean),
        .o_icache_clean         (o_icache_clean),
        .o_icache_clean         (o_icache_clean),
        .o_dtlb_inv             (o_dtlb_inv),
        .o_dtlb_inv             (o_dtlb_inv),
Line 1208... Line 1176...
        .i_icache_inv_done      (i_icache_inv_done),
        .i_icache_inv_done      (i_icache_inv_done),
        .i_dcache_clean_done    (i_dcache_clean_done),
        .i_dcache_clean_done    (i_dcache_clean_done),
        .i_icache_clean_done    (i_icache_clean_done)
        .i_icache_clean_done    (i_icache_clean_done)
);
);
 
 
`ifndef SYNTHESIS
 
 
 
reg [(8*8)-1:0] CPU_MODE; // Max 8 characters i.e. 64-bit string.
reg [(8*8)-1:0] CPU_MODE; // Max 8 characters i.e. 64-bit string.
 
 
always @*
always @*
case(o_cpsr[`CPSR_MODE])
case(o_cpsr[`CPSR_MODE])
FIQ: CPU_MODE = "FIQ";
FIQ: CPU_MODE = "FIQ";
Line 1221... Line 1187...
USR: CPU_MODE = "USR";
USR: CPU_MODE = "USR";
UND: CPU_MODE = "UND";
UND: CPU_MODE = "UND";
SVC: CPU_MODE = "SVC";
SVC: CPU_MODE = "SVC";
ABT: CPU_MODE = "ABT";
ABT: CPU_MODE = "ABT";
SYS: CPU_MODE = "SYS";
SYS: CPU_MODE = "SYS";
 
default: CPU_MODE = "???";
endcase
endcase
 
 
`endif
 
 
 
endmodule // zap_core.v
endmodule // zap_core.v
 
 
`default_nettype wire
`default_nettype wire
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.