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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_predecode_coproc.v] - Diff between revs 26 and 38

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Rev 26 Rev 38
Line 111... Line 111...
wire c2 = i_cpsr_ff_mode != USR;
wire c2 = i_cpsr_ff_mode != USR;
wire c3 = i_instruction[11:8] == 4'b1111;
wire c3 = i_instruction[11:8] == 4'b1111;
wire c4 = i_instruction[34:32] == 3'd0;
wire c4 = i_instruction[34:32] == 3'd0;
wire c5 = c1 & c2 & c3 & c4;
wire c5 = c1 & c2 & c3 & c4;
 
 
 
`ifndef SYNTHESIS
 
 
 
reg eclass;
 
 
 
`endif
 
 
// Next state logic.
// Next state logic.
always @*
always @*
begin
begin
        // Default values.
        // Default values.
        cp_dav_nxt              = cp_dav_ff;
        cp_dav_nxt              = cp_dav_ff;
Line 124... Line 130...
        o_valid                 = i_valid;
        o_valid                 = i_valid;
        state_nxt               = state_ff;
        state_nxt               = state_ff;
        o_irq                   = i_irq;
        o_irq                   = i_irq;
        o_fiq                   = i_fiq;
        o_fiq                   = i_fiq;
 
 
 
        `ifndef SYNTHESIS
 
                eclass = 0;
 
        `endif
 
 
        case ( state_ff )
        case ( state_ff )
        IDLE:
        IDLE:
                // Activate only if no thumb, not in USER mode and CP15 access is requested.
                // Activate only if no thumb, not in USER mode and CP15 access is requested.
                casez ( (!i_cpsr_ff_t && (i_cpsr_ff_mode != USR) & (i_instruction[11:8] == 4'b1111) & (i_instruction[34:32] == 3'd0)) ? i_instruction[31:0] : 35'd0 )
                casez ( (!i_cpsr_ff_t && (i_instruction[34:32] == 3'd0) && i_valid) ? i_instruction[31:0] : 35'd0 )
                MRC, MCR, LDC, STC, CDP:
                MRC, MCR, LDC, STC, CDP:
                begin
                begin
 
                        if ( i_instruction[11:8] == 4'b1111 && i_cpsr_ff_mode != USR )  // CP15 and root access -- perfectly fine.
 
                        begin
                        // Send ANDNV R0, R0, R0 instruction.
                        // Send ANDNV R0, R0, R0 instruction.
                        o_instruction = {4'b1111, 28'd0};
                        o_instruction = {4'b1111, 28'd0};
                        o_valid       = 1'd0;
                        o_valid       = 1'd0;
                        o_irq         = 1'd0;
                        o_irq         = 1'd0;
                        o_fiq         = 1'd0;
                        o_fiq         = 1'd0;
Line 158... Line 170...
                                cp_word_nxt             = i_instruction;
                                cp_word_nxt             = i_instruction;
                                cp_dav_nxt              = 1'd1;
                                cp_dav_nxt              = 1'd1;
                                state_nxt               = BUSY;
                                state_nxt               = BUSY;
                        end
                        end
                end
                end
 
                        else // Warning...
 
                        begin
 
                                `ifndef SYNTHESIS
 
 
 
                                if ( i_instruction[11:8] != 4'b1111 )
 
                                        eclass = 1;
 
                                else
 
                                        eclass = 2;
 
 
 
                                `endif
 
 
 
                                // Remain transparent since this is not a coprocessor
 
                                // instruction.
 
                                o_valid                 = i_valid;
 
                                o_instruction           = i_instruction;
 
                                o_irq                   = i_irq;
 
                                o_fiq                   = i_fiq;
 
                                cp_dav_nxt              = 0;
 
                                o_stall_from_decode     = 0;
 
                                cp_word_nxt             = {32{1'dx}}; // Don't care.
 
                        end
 
                end
                default:
                default:
                begin
                begin
                        // Remain transparent since this is not a coprocessor
                        // Remain transparent since this is not a coprocessor
                        // instruction.
                        // instruction.
                        o_valid                 = i_valid;
                        o_valid                 = i_valid;

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