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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_predecode_mem_fsm.v] - Diff between revs 37 and 38

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Rev 37 Rev 38
Line 200... Line 200...
                BLX1_ARM_S4:
                BLX1_ARM_S4:
                begin
                begin
                        o_stall_from_decode = 1'd1;
                        o_stall_from_decode = 1'd1;
 
 
                        // ORR DUMMY0, DUMMY0, 1 - Needed to indicate a switch
                        // ORR DUMMY0, DUMMY0, 1 - Needed to indicate a switch
                        // to Thumb.                       
                        // to Thumb if needed.                       
                         o_instruction[31:0] = {AL, 2'b00, 1'b1, ORR, 1'd0, 4'd0, 4'd0, 4'd0, !i_cpsr_t};
                         o_instruction[31:0] = {AL, 2'b00, 1'b1, ORR, 1'd0, 4'd0, 4'd0, 4'd0, !i_cpsr_t};
                        {o_instruction[`DP_RD_EXTEND], o_instruction[`DP_RD]} = ARCH_DUMMY_REG0;
                        {o_instruction[`DP_RD_EXTEND], o_instruction[`DP_RD]} = ARCH_DUMMY_REG0;
                        {o_instruction[`DP_RA_EXTEND], o_instruction[`DP_RA]} = ARCH_DUMMY_REG0;
                        {o_instruction[`DP_RA_EXTEND], o_instruction[`DP_RA]} = ARCH_DUMMY_REG0;
                end
                end
 
 
Line 233... Line 233...
                begin
                begin
                        // BLX1 detected. Unconditional!!!
                        // BLX1 detected. Unconditional!!!
                        // Immediate Offset.
                        // Immediate Offset.
                        if ( i_instruction[31:25] == BLX1[31:25] && i_instruction_valid )
                        if ( i_instruction[31:25] == BLX1[31:25] && i_instruction_valid )
                        begin
                        begin
`ifdef LDM_DEBUG
 
                                $display($time, "%m: BLX1 detected!");
                                $display($time, "%m: BLX1 detected!");
`endif
 
                                // We must generate a SUBAL LR,PC,4 ROR 0
                                // We must generate a SUBAL LR,PC,4 ROR 0
                                // This makes LR have the value
                                // This makes LR have the value
                                // PC+8-4=PC+4 which is the address of
                                // PC+8-4=PC+4 which is the address of
                                // the next instruction.
                                // the next instruction.
                                o_instruction           = {AL, 2'b00, 1'b1, SUB, 1'd0, 4'd14, 4'd15, 12'd4};
                                o_instruction           = {AL, 2'b00, 1'b1, SUB, 1'd0, 4'd14, 4'd15, 12'd4};
Line 253... Line 252...
                                o_stall_from_decode     = 1'd1; // Stall the core.
                                o_stall_from_decode     = 1'd1; // Stall the core.
                                state_nxt               = BLX1_ARM_S0;
                                state_nxt               = BLX1_ARM_S0;
                        end
                        end
                        else if ( i_instruction[27:4] == BLX2[27:4] && i_instruction_valid ) // BLX2 detected. Register offset. CONDITIONAL.
                        else if ( i_instruction[27:4] == BLX2[27:4] && i_instruction_valid ) // BLX2 detected. Register offset. CONDITIONAL.
                        begin
                        begin
`ifdef LDM_DEBUG
 
                                $display($time, "%m: BLX2 detected!");
                                $display($time, "%m: BLX2 detected!");
`endif
 
                                // Write address of next instruction to LR. Now this
                                // Write address of next instruction to LR. Now this
                                // depends on the mode we're in. Mode in the sense
                                // depends on the mode we're in. Mode in the sense
                                // ARM/Thumb. We need to look at i_cpsr_t.
                                // ARM/Thumb. We need to look at i_cpsr_t.
 
 
                                // We need to generate a SUBcc LR,PC,4 ROR 0
                                // We need to generate a SUBcc LR,PC,4 ROR 0

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