OpenCores
URL https://opencores.org/ocsvn/zap/zap/trunk

Subversion Repositories zap

[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_register_file.v] - Diff between revs 43 and 51

Show entire file | Details | Blame | View Log

Rev 43 Rev 51
Line 68... Line 68...
        end
        end
end
end
 
 
reg [39:0] sel;
reg [39:0] sel;
 
 
// assertions_start
 
        wire [31:0] r0;  assign r0 =  sel[0]  ? MEM[0] : mem[0];
        wire [31:0] r0;  assign r0 =  sel[0]  ? MEM[0] : mem[0];
        wire [31:0] r1;  assign r1 =  sel[1]  ? MEM[1] : mem[1];
        wire [31:0] r1;  assign r1 =  sel[1]  ? MEM[1] : mem[1];
        wire [31:0] r2;  assign r2 =  sel[2]  ? MEM[2] : mem[2];
        wire [31:0] r2;  assign r2 =  sel[2]  ? MEM[2] : mem[2];
        wire [31:0] r3;  assign r3 =  sel[3]  ? MEM[3] : mem[3];
        wire [31:0] r3;  assign r3 =  sel[3]  ? MEM[3] : mem[3];
        wire [31:0] r4;  assign r4 =  sel[4]  ? MEM[4] : mem[4];
        wire [31:0] r4;  assign r4 =  sel[4]  ? MEM[4] : mem[4];
Line 109... Line 108...
        wire [31:0] r35; assign r35 = sel[35] ? MEM[35] : mem[35];
        wire [31:0] r35; assign r35 = sel[35] ? MEM[35] : mem[35];
        wire [31:0] r36; assign r36 = sel[36] ? MEM[36] : mem[36];
        wire [31:0] r36; assign r36 = sel[36] ? MEM[36] : mem[36];
        wire [31:0] r37; assign r37 = sel[37] ? MEM[37] : mem[37];
        wire [31:0] r37; assign r37 = sel[37] ? MEM[37] : mem[37];
        wire [31:0] r38; assign r38 = sel[38] ? MEM[38] : mem[38];
        wire [31:0] r38; assign r38 = sel[38] ? MEM[38] : mem[38];
        wire [31:0] r39; assign r39 = sel[39] ? MEM[39] : mem[39];
        wire [31:0] r39; assign r39 = sel[39] ? MEM[39] : mem[39];
// assertions_end
 
 
 
always @ (posedge i_clk)
always @ (posedge i_clk)
begin
begin
        if ( i_reset )
        if ( i_reset )
        begin
        begin
Line 142... Line 140...
        o_rd_data_c = sel[i_rd_addr_c] ? MEM [ i_rd_addr_c ] : mem [ i_rd_addr_c ];
        o_rd_data_c = sel[i_rd_addr_c] ? MEM [ i_rd_addr_c ] : mem [ i_rd_addr_c ];
        o_rd_data_d = sel[i_rd_addr_d] ? MEM [ i_rd_addr_d ] : mem [ i_rd_addr_d ];
        o_rd_data_d = sel[i_rd_addr_d] ? MEM [ i_rd_addr_d ] : mem [ i_rd_addr_d ];
end
end
 
 
endmodule // bram_wrapper.v
endmodule // bram_wrapper.v
 
 
`default_nettype wire
`default_nettype wire
 
 
 No newline at end of file
 No newline at end of file
 
// ----------------------------------------------------------------------------
 
// EOF
 
// ----------------------------------------------------------------------------
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.