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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_tlb_check.v] - Diff between revs 28 and 51

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Rev 28 Rev 51
Line 87... Line 87...
output reg [7:0]                        o_fsr;          // FSR. 0 means all OK.
output reg [7:0]                        o_fsr;          // FSR. 0 means all OK.
output reg [31:0]                       o_far;          // Fault Address Register.
output reg [31:0]                       o_far;          // Fault Address Register.
output reg                              o_cacheable;    // Cacheble stats of the PTE.
output reg                              o_cacheable;    // Cacheble stats of the PTE.
output reg [31:0]                       o_phy_addr;     // Physical address.
output reg [31:0]                       o_phy_addr;     // Physical address.
 
 
 
// ----------------------------------------------------------------------------
 
 
always @*
always @*
begin
begin
 
 
        // Default values. Taken for MMU disabled esp.
        // Default values. Taken for MMU disabled esp.
        o_fsr       = 0;        // No fault.
        o_fsr       = 0;        // No fault.
        o_far       = i_va;     // Fault address.
        o_far       = i_va;     // Fault address.
        o_phy_addr  = i_va;     // VA = PA
        o_phy_addr  = i_va;     // VA = PA
        o_walk      = 0;        // Walk disabled.
        o_walk      = 0;        // Walk disabled.
Line 250... Line 251...
        // Assign to function. Return.
        // Assign to function. Return.
        is_apsr_ok = x;
        is_apsr_ok = x;
end
end
endfunction
endfunction
 
 
 
 
endmodule // zap_tlb_check.v
endmodule // zap_tlb_check.v
 
 
`default_nettype wire
`default_nettype wire
 
 
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// ----------------------------------------------------------------------------
 
// EOF
 
// ----------------------------------------------------------------------------
 
 
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