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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_top.v] - Diff between revs 34 and 43

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Line 29... Line 29...
 
 
`default_nettype none
`default_nettype none
 
 
module zap_top #(
module zap_top #(
 
 
// Enable cache and MMU.
// -----------------------------------
 
// BP entries, FIFO depths
 
// -----------------------------------
 
 
parameter               BP_ENTRIES              = 1024, // Predictor depth.
parameter               BP_ENTRIES              = 1024, // Predictor depth.
parameter               FIFO_DEPTH              = 4,    // FIFO depth.
parameter               FIFO_DEPTH              = 4,    // FIFO depth.
parameter               STORE_BUFFER_DEPTH      = 16,   // Depth of the store buffer.
parameter               STORE_BUFFER_DEPTH      = 16,   // Depth of the store buffer.
 
 
// ----------------------------------
// ----------------------------------
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parameter [31:0] CODE_LPAGE_TLB_ENTRIES   =  32'd8,    // Large page TLB entries.
parameter [31:0] CODE_LPAGE_TLB_ENTRIES   =  32'd8,    // Large page TLB entries.
parameter [31:0] CODE_SPAGE_TLB_ENTRIES   =  32'd16,   // Small page TLB entries.
parameter [31:0] CODE_SPAGE_TLB_ENTRIES   =  32'd16,   // Small page TLB entries.
parameter [31:0] CODE_CACHE_SIZE          =  32'd1024  // Cache size in bytes.
parameter [31:0] CODE_CACHE_SIZE          =  32'd1024  // Cache size in bytes.
 
 
)(
)(
        // Clock. CPU uses posedge synchronous design.
        // --------------------------------------
        input   wire            i_clk,
        // Clock and reset
 
        // --------------------------------------
 
 
        // Active high and synchronous. Must be clean and synchronous.
        input   wire            i_clk,
        input   wire            i_reset,
        input   wire            i_reset,
 
 
 
        // ---------------------------------------
        // Interrupts. 
        // Interrupts. 
        // Both of them are active high and level trigerred.
        // Both of them are active high and level 
 
        // trigerred.
 
        // ---------------------------------------
 
 
        input   wire            i_irq,
        input   wire            i_irq,
        input   wire            i_fiq,
        input   wire            i_fiq,
 
 
        // ---------------------
        // ---------------------
        // Wishbone interface.
        // Wishbone interface.
        // ---------------------
        // ---------------------
 
 
        output  wire            o_wb_cyc,
        output  wire            o_wb_cyc,
        output  wire            o_wb_stb,
        output  wire            o_wb_stb,
 
        output  wire            o_wb_stb_nxt,
 
        output  wire            o_wb_cyc_nxt,
 
        output wire  [31:0]     o_wb_adr_nxt,
        output  wire [31:0]     o_wb_adr,
        output  wire [31:0]     o_wb_adr,
        output  wire            o_wb_we,
        output  wire            o_wb_we,
        output wire  [31:0]     o_wb_dat,
        output wire  [31:0]     o_wb_dat,
        output  wire [3:0]      o_wb_sel,
        output  wire [3:0]      o_wb_sel,
        output wire [2:0]       o_wb_cti,
        output wire [2:0]       o_wb_cti,
Line 91... Line 103...
wire [3:0] wb_sel;
wire [3:0] wb_sel;
wire [31:0] wb_dat, wb_idat;
wire [31:0] wb_dat, wb_idat;
wire [31:0] wb_adr;
wire [31:0] wb_adr;
wire [2:0] wb_cti;
wire [2:0] wb_cti;
wire wb_ack;
wire wb_ack;
 
reg             reset;
 
 
reg reset;       // Drives global reset throughout the CPU.
// Synchronous reset signal flopped.
 
 
//
 
// Reset synchrnonizer is assumed to be external to the CPU.
 
// * EXTERNAL RESET MUST BE CLEAN AND SYNCHRONOUS *
 
//
 
always @ (posedge i_clk)
always @ (posedge i_clk)
begin
 
        reset    <= i_reset;
        reset    <= i_reset;
end
 
 
 
wire cpu_mmu_en;
wire cpu_mmu_en;
wire [31:0] cpu_cpsr;
wire [31:0] cpu_cpsr;
wire cpu_mem_translate;
wire cpu_mem_translate;
 
 
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wire [31:0] dc_far;
wire [31:0] dc_far;
 
 
wire cpu_dc_en, cpu_ic_en;
wire cpu_dc_en, cpu_ic_en;
 
 
wire [1:0] cpu_sr;
wire [1:0] cpu_sr;
 
wire [7:0]      cpu_pid;
wire [31:0] cpu_baddr, cpu_dac_reg;
wire [31:0] cpu_baddr, cpu_dac_reg;
 
 
wire cpu_dc_inv, cpu_ic_inv;
wire cpu_dc_inv, cpu_ic_inv;
wire cpu_dc_clean, cpu_ic_clean;
wire cpu_dc_clean, cpu_ic_clean;
 
 
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.i_far                  (dc_far),
.i_far                  (dc_far),
.o_dac                  (cpu_dac_reg),
.o_dac                  (cpu_dac_reg),
.o_baddr                (cpu_baddr),
.o_baddr                (cpu_baddr),
.o_mmu_en               (cpu_mmu_en),
.o_mmu_en               (cpu_mmu_en),
.o_sr                   (cpu_sr),
.o_sr                   (cpu_sr),
 
.o_pid                  (cpu_pid),
.o_dcache_inv           (cpu_dc_inv),
.o_dcache_inv           (cpu_dc_inv),
.o_icache_inv           (cpu_ic_inv),
.o_icache_inv           (cpu_ic_inv),
.o_dcache_clean         (cpu_dc_clean),
.o_dcache_clean         (cpu_dc_clean),
.o_icache_clean         (cpu_ic_clean),
.o_icache_clean         (cpu_ic_clean),
.o_dtlb_inv             (cpu_dtlb_inv),
.o_dtlb_inv             (cpu_dtlb_inv),
Line 210... Line 218...
.i_dcache_clean_done    (dc_clean_done),
.i_dcache_clean_done    (dc_clean_done),
.i_icache_clean_done    (ic_clean_done),
.i_icache_clean_done    (ic_clean_done),
.o_dcache_en            (cpu_dc_en),
.o_dcache_en            (cpu_dc_en),
.o_icache_en            (cpu_ic_en),
.o_icache_en            (cpu_ic_en),
 
 
// Combo Outputs - UNUSED.
 
.o_clear_from_alu       (),
 
.o_stall_from_shifter   (),
 
.o_stall_from_issue     (),
 
.o_stall_from_decode    (),
 
.o_clear_from_decode    (),
 
.o_clear_from_writeback (),
 
 
 
// Data IF nxt.
// Data IF nxt.
.o_data_wb_adr_nxt     (cpu_daddr_nxt), // Data addr nxt. Used to drive address of data tag RAM.
.o_data_wb_adr_nxt     (cpu_daddr_nxt), // Data addr nxt. Used to drive address of data tag RAM.
.o_data_wb_we_nxt       (),
.o_data_wb_we_nxt       (),
.o_data_wb_cyc_nxt      (),
.o_data_wb_cyc_nxt      (),
.o_data_wb_stb_nxt      (),
.o_data_wb_stb_nxt      (),
Line 234... Line 234...
 
 
.o_cpsr                 (cpu_cpsr)
.o_cpsr                 (cpu_cpsr)
 
 
);
);
 
 
zap_cache #(.CACHE_SIZE(DATA_CACHE_SIZE),
zap_cache #(
 
        .CACHE_SIZE(DATA_CACHE_SIZE),
.SPAGE_TLB_ENTRIES(DATA_SPAGE_TLB_ENTRIES),
.SPAGE_TLB_ENTRIES(DATA_SPAGE_TLB_ENTRIES),
.LPAGE_TLB_ENTRIES(DATA_LPAGE_TLB_ENTRIES),
.LPAGE_TLB_ENTRIES(DATA_LPAGE_TLB_ENTRIES),
.SECTION_TLB_ENTRIES(DATA_SECTION_TLB_ENTRIES))
.SECTION_TLB_ENTRIES(DATA_SECTION_TLB_ENTRIES))
u_data_cache (
u_data_cache (
.i_clk          (i_clk),
.i_clk          (i_clk),
.i_reset        (reset),
.i_reset        (reset),
.i_address      (cpu_daddr),
.i_address              (cpu_daddr + (cpu_pid << 25)),
.i_address_nxt  (cpu_daddr_nxt),
.i_address_nxt          (cpu_daddr_nxt + (cpu_pid << 25)),
 
 
.i_rd           (!cpu_dc_we && cpu_dc_stb),
.i_rd           (!cpu_dc_we && cpu_dc_stb),
.i_wr           (cpu_dc_we),
.i_wr           (cpu_dc_we),
.i_ben          (cpu_dc_sel),
.i_ben          (cpu_dc_sel),
.i_dat          (cpu_dc_dat),
.i_dat          (cpu_dc_dat),
Line 294... Line 295...
.LPAGE_TLB_ENTRIES(CODE_LPAGE_TLB_ENTRIES),
.LPAGE_TLB_ENTRIES(CODE_LPAGE_TLB_ENTRIES),
.SECTION_TLB_ENTRIES(CODE_SECTION_TLB_ENTRIES))
.SECTION_TLB_ENTRIES(CODE_SECTION_TLB_ENTRIES))
u_code_cache (
u_code_cache (
.i_clk              (i_clk),
.i_clk              (i_clk),
.i_reset            (reset),
.i_reset            (reset),
.i_address          (cpu_iaddr     & 32'hFFFF_FFFC), // Cut off lower 2 bits.
.i_address          ((cpu_iaddr     & 32'hFFFF_FFFC) + (cpu_pid << 25)), // Cut off lower 2 bits.
.i_address_nxt      (cpu_iaddr_nxt & 32'hFFFF_FFFC), // Cut off lower 2 bits.
.i_address_nxt      ((cpu_iaddr_nxt & 32'hFFFF_FFFC) + (cpu_pid << 25)), // Cut off lower 2 bits.
 
 
.i_rd              (cpu_instr_stb),
.i_rd              (cpu_instr_stb),
.i_wr              (1'd0),
.i_wr              (1'd0),
.i_ben             (4'b1111),
.i_ben             (4'b1111),
.i_dat             (32'd0),
.i_dat             (32'd0),
.o_dat             (ic_data),
.o_dat             (ic_data),
.o_ack             (instr_ack),
.o_ack             (instr_ack),
.o_err             (instr_err),
.o_err             (instr_err),
 
 
.o_fsr(), // UNCONNO.
.o_fsr             (),
.o_far(), // UNCONNO.
.o_far             (),
.i_mmu_en          (cpu_mmu_en),
.i_mmu_en          (cpu_mmu_en),
.i_cache_en        (cpu_ic_en),
.i_cache_en        (cpu_ic_en),
.i_cache_inv_req   (cpu_ic_inv),
.i_cache_inv_req   (cpu_ic_inv),
.i_cache_clean_req (cpu_ic_clean),
.i_cache_clean_req (cpu_ic_clean),
.o_cache_inv_done  (ic_inv_done),
.o_cache_inv_done  (ic_inv_done),
Line 395... Line 396...
.o_wb_sel(o_wb_sel),
.o_wb_sel(o_wb_sel),
.o_wb_dat(o_wb_dat),
.o_wb_dat(o_wb_dat),
.o_wb_adr(o_wb_adr),
.o_wb_adr(o_wb_adr),
.o_wb_cti(o_wb_cti),
.o_wb_cti(o_wb_cti),
.i_wb_dat(i_wb_dat),
.i_wb_dat(i_wb_dat),
.i_wb_ack(i_wb_ack)
.i_wb_ack(i_wb_ack),
 
 
 
// CYC and STB nxt.
 
.o_wb_stb_nxt (o_wb_stb_nxt),
 
.o_wb_cyc_nxt (o_wb_cyc_nxt),
 
.o_wb_adr_nxt (o_wb_adr_nxt),
 
.o_wb_sel_nxt (),
 
.o_wb_dat_nxt (),
 
.o_wb_we_nxt  ()
);
);
 
 
endmodule // zap_top.v
endmodule // zap_top.v
 
 
`default_nettype wire
`default_nettype wire
 
 
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