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[/] [zap/] [trunk/] [src/] [ts/] [arm_test/] [Config.cfg] - Diff between revs 38 and 43

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Rev 38 Rev 43
Line 14... Line 14...
        INSTR_FIFO_DEPTH            => 4,       # Instruction buffer depth.
        INSTR_FIFO_DEPTH            => 4,       # Instruction buffer depth.
        STORE_BUFFER_DEPTH          => 16,      # Store buffer depth.
        STORE_BUFFER_DEPTH          => 16,      # Store buffer depth.
        SYNTHESIS                   => 0,       # 0 allows debug messages.
        SYNTHESIS                   => 0,       # 0 allows debug messages.
 
 
        # Testbench configuration.
        # Testbench configuration.
        IRQ_EN                      => 0,
        WAVES                       => 0,       # Log VCD
        UART_TX_TERMINAL            => 0,       # Disable UART TX terminal.
 
        EXT_RAM_SIZE                => 32768,   # External RAM size.
        EXT_RAM_SIZE                => 32768,   # External RAM size.
        SEED                        => -1,      # Seed. Use -1 to use random seed.
        SEED                        => -1,      # Seed. Use -1 to use random seed.
        DUMP_START                  => 2000,    # Starting memory address from which to dump.
        DUMP_START                  => 2000,    # Starting memory address from which to dump.
        DUMP_SIZE                   => 200,     # Length of dump in bytes.
        DUMP_SIZE                   => 200,     # Length of dump in bytes.
        MAX_CLOCK_CYCLES            => 100000,  # Clock cycles to run the simulation for.
        MAX_CLOCK_CYCLES            => 40000,   # Clock cycles to run the simulation for.
        ALLOW_STALLS                => 1,       # Make this 1 to allow external RAM to signal a stall.
 
        DEFINE_TLB_DEBUG            => 0,       # Make this 1 to define TLB_DEBUG. Useful for debugging the TLB.
        DEFINE_TLB_DEBUG            => 0,       # Make this 1 to define TLB_DEBUG. Useful for debugging the TLB.
        REG_CHECK                   => {
        REG_CHECK                   => {
                                                # Value of registers(Post Translate) at the end of the test.
                                                # Value of registers(Post Translate) at the end of the test.
                                                # "r => Verilog_value"
                                                # "r => Verilog_value"
                                                "r0"  => "32'hFFFFFFFF",
                                                "r0"  => "32'hFFFFFFFF",

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