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[/] [zap/] [trunk/] [src/] [ts/] [factorial/] [Config.cfg] - Diff between revs 34 and 38

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Rev 34 Rev 38
Line 14... Line 14...
        INSTR_FIFO_DEPTH            => 4,       # Instruction buffer depth.
        INSTR_FIFO_DEPTH            => 4,       # Instruction buffer depth.
        STORE_BUFFER_DEPTH          => 16,      # Store buffer depth.
        STORE_BUFFER_DEPTH          => 16,      # Store buffer depth.
        SYNTHESIS                   => 0,       # 0 allows debug messages.
        SYNTHESIS                   => 0,       # 0 allows debug messages.
 
 
        # Testbench configuration.
        # Testbench configuration.
        UART_TX_TERMINAL            => 0,
        IRQ_EN                      => 1,       # Enable IRQs.
 
        UART_TX_TERMINAL            => 0,       # No UART terminal.
        EXT_RAM_SIZE                => 32768,   # External RAM size.
        EXT_RAM_SIZE                => 32768,   # External RAM size.
        SEED                        => -1,      # Seed. Use -1 to use random seed.
        SEED                        => -1,      # Seed. Use -1 to use random seed.
        DUMP_START                  => 2000,    # Starting memory address from which to dump.
        DUMP_START                  => 2000,    # Starting memory address from which to dump.
        DUMP_SIZE                   => 200,     # Length of dump in bytes.
        DUMP_SIZE                   => 200,     # Length of dump in bytes.
        MAX_CLOCK_CYCLES            => 100000,  # Clock cycles to run the simulation for.
        MAX_CLOCK_CYCLES            => 100000,  # Clock cycles to run the simulation for.
        ALLOW_STALLS                => 1,       # Make this 1 to allow external RAM to signal a stall.
        ALLOW_STALLS                => 0,       # Make this 1 to allow external RAM to signal a stall.
        DEFINE_TLB_DEBUG            => 0,       # Make this 1 to define TLB_DEBUG. Useful for debugging the TLB.
        DEFINE_TLB_DEBUG            => 0,       # Make this 1 to define TLB_DEBUG. Useful for debugging the TLB.
        REG_CHECK                   => {},      # Registers to examine.
        REG_CHECK                   => {},      # Registers to examine.
        FINAL_CHECK                 => {
        FINAL_CHECK                 => {
                                                # Values of memory for test to succeed.
                                                # Values of memory for test to succeed.
                                                # LOCATION => VALUE
                                                # LOCATION => VALUE

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