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[/] [zap/] [trunk/] [src/] [ts/] [factorial/] [factorial.s] - Diff between revs 38 and 43

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Rev 38 Rev 43
Line 57... Line 57...
mov r10, #12
mov r10, #12
mov r11, #13
mov r11, #13
mov r12, #14
mov r12, #14
mov r14, #15
mov r14, #15
 
 
 
.set TIMER_BASE_ADDRESS, 0xFFFFFFC0
 
 
# Restart timer
# Restart timer
ldr r0 ,=#0xFFFFFFC0    // Timer base address.
ldr r0,=TIMER_BASE_ADDRESS    // Timer base address.
add r0, r0, #12
add r0, r0, #12
ldr r1, =#0x1
mov r1, #1
str r1, [r0]            // Restart the timer.
str r1, [r0]            // Restart the timer.
 
 
 
.set VIC_BASE_ADDRESS,  0xFFFFFFA0
 
.set CLEAR_ALL_PENDING, 0xFFFFFFFF
 
 
# Clear interrupt in VIC.
# Clear interrupt in VIC.
ldr r0, =#0xFFFFFFA0    // VIC base address
ldr r0, =VIC_BASE_ADDRESS   // VIC base address
add r0, r0, #8
add r0, r0, #8
ldr r1, =#0xFFFFFFFF
ldr r1, =CLEAR_ALL_PENDING
str r1, [r0]            // Clear all interrupt pending status
str r1, [r0]            // Clear all interrupt pending status
 
 
 
# Restore
ldmfd sp!, {r0-r12, pc}^
ldmfd sp!, {r0-r12, pc}^
 
 
FIQ:
FIQ:
# Return from FIQ after writing to FIQ registers.
# Return from FIQ after writing to FIQ registers - shouldn't affect other things.
mov r8,  #9
mov r8,  #9
mov r9,  #10
mov r9,  #10
mov r10, #12
mov r10, #12
mov r11, #13
mov r11, #13
mov r12, #14
mov r12, #14
mov r8, #0
subs pc, r14, #4
mov r9, #0
 
mov r10, #0
SWI:
mov r11, #10
.set SWI_SP_VALUE,  2500
mov r12, #0
.set SWI_R11_VALUE, 2004
subs pc, r14, #4
ldr sp,=SWI_SP_VALUE
 
ldr r11,=SWI_R11_VALUE
SWI:
mov r0, #12
ldr sp,=#2500
mov r1, #0
ldr r11, =#2004
mov r2, r0, lsr #32
mov r0, #12
mov r3, r0, lsr r1
mov r1, #0
mov r4, #-1
mov r2, r0, lsr #32
mov r5, #-1
mov r3, r0, lsr r1
muls r6, r5, r4
mov r4, #-1
umull r8,  r7, r5, r4
mov r5, #-1
smull r10, r9, r5, r4
muls r6, r5, r4
mov r2, r10
umull r8,  r7, r5, r4
str r10, [r11, #4]!
smull r10, r9, r5, r4
str r9,  [r11, #4]!
mov r2, r10
add r11, r11, #4
str r10, [r11, #4]!
str r8,  [r11], #4
str r9,  [r11, #4]!
str r7,  [r11], #4
add r11, r11, #4
str r6,  [r11]
str r8,  [r11], #4
stmib r11, {r6-r10}
str r7,  [r11], #4
stmfd sp!, {r0-r12, r14}
str r6,  [r11]
mrs r1, spsr
stmib r11, {r6-r10}
orr r1, r1, #0x80
stmfd sp!, {r0-r12, r14}
msr spsr_c, r1
mrs r1, spsr
mov r4, #0
orr r1, r1, #0x80
mcr p15, 0, r4, c7, c15, 0
msr spsr_c, r1
mov r4, #-1
mov r4, #0
ldmfd sp!, {r0-r12, pc}^
mcr p15, 0, r4, c7, c15, 0
 
mov r4, #-1
there:
ldmfd sp!, {r0-r12, pc}^
// Switch to IRQ mode.
 
mrs r2, cpsr
there:
bic r2, r2, #31
// Switch to IRQ mode.
orr r2, r2, #18
mrs r2, cpsr
msr cpsr_c, r2
bic r2, r2, #31
 
orr r2, r2, #18
.set IRQ_SP_VALUE, 3000
msr cpsr_c, r2
ldr sp,=IRQ_SP_VALUE
ldr sp, =#3000
 
 
// Switch to UND mode.
// Switch to UND mode.
mrs r3, cpsr
mrs r3, cpsr
bic r3, r3, #31
bic r3, r3, #31
orr r3, r3, #27
orr r3, r3, #27
msr cpsr_c, r3
msr cpsr_c, r3
mov r4, #1
mov r4, #1
 
ldr sp, =#3500
.set UND_SP_VALUE, 3500
 
ldr sp, =UND_SP_VALUE
// Enable interrupts (FIQ and IRQ).
 
mrs r1, cpsr
// Enable interrupts (FIQ and IRQ).
bic r1, r1, #0xC0
mrs r1, cpsr
msr cpsr_c, r1
bic r1, r1, #0xC0
 
msr cpsr_c, r1
// Enable cache (Uses a single bit to enable both caches).
 
ldr r1, =#4100
// Enable cache (Uses a single bit to enable both caches).
mcr p15, 0, r1, c1, c1, 0
.set ENABLE_CACHE_CP_WORD, 4100
 
ldr r1, =ENABLE_CACHE_CP_WORD
// Write out identitiy section mapping. Write 16KB to register 2.
mcr p15, 0, r1, c1, c1, 0
mov r1, #1
 
mov r1, r1, lsl #14
// Write out identitiy section mapping. Write 16KB to register 2.
mcr p15, 0, r1, c2, c0, 1
mov r1, #1
 
mov r1, r1, lsl #14
// Set domain access control to all 1s.
mcr p15, 0, r1, c2, c0, 1
mvn r1, #0
 
mcr p15, 0, r1, c3, c0, 0
// Set domain access control to all 1s.
 
mvn r1, #0
// Set up a section desctiptor for identity mapping that is Cachaeable.
mcr p15, 0, r1, c3, c0, 0
mov r1, #1
 
mov r1, r1, lsl #14     // 16KB
// Set up a section desctiptor for identity mapping that is Cachaeable.
mov r2, #14             // Cacheable identity descriptor.
mov r1, #1
str r2, [r1]            // Write identity section desctiptor to 16KB location.
mov r1, r1, lsl #14     // 16KB
ldr r6, [r1]            // R6 holds the descriptor.
mov r2, #14             // Cacheable identity descriptor.
mov r7, r1              // R7 holds the address.
str r2, [r1]            // Write identity section desctiptor to 16KB location.
 
ldr r6, [r1]            // R6 holds the descriptor.
// Set up a section descriptor for upper 1MB of virtual address space.
mov r7, r1              // R7 holds the address.
// This is identity mapping. Uncacheable.
 
mov r1, #1
// Set up a section descriptor for upper 1MB of virtual address space.
mov r1, r1, lsl #14     // 16KB. This is descriptor 0.
// This is identity mapping. Uncacheable.
// Go to descriptor 4095. This is the address BASE + (#DESC * 4).
mov r1, #1
ldr r2,=#16380
mov r1, r1, lsl #14     // 16KB. This is descriptor 0.
add r1, r1, r2
 
// Prepare a descriptor. Descriptor = 0xFFF00002 (Uncacheable section descriptor).
// Go to descriptor 4095. This is the address BASE + (#DESC * 4).
ldr r2 ,=#0xFFF00002
.set DESCRIPTOR_IO_SECTION_OFFSET, 16380 // 4095 x 4
str r2, [r1]
ldr r2,=DESCRIPTOR_IO_SECTION_OFFSET
ldr r6, [r1]
add r1, r1, r2
mov r7, r1
 
 
// Prepare a descriptor. Descriptor = 0xFFF00002 (Uncacheable section descriptor).
// ENABLE MMU
.set DESCRIPTOR_IO_SECTION, 0xFFF00002
ldr r1, =#4101
ldr r2 ,=DESCRIPTOR_IO_SECTION
mcr p15, 0, r1, c1, c1, 0
str r2, [r1]
 
ldr r6, [r1]
// Switch mode.
mov r7, r1
mrs r2, cpsr
 
bic r2, r2, #31
// ENABLE MMU
orr r2, r2, #16
.set ENABLE_MMU_CP_WORD, 4101
msr cpsr_c, r2
ldr r1, =ENABLE_MMU_CP_WORD
ldr sp,=#3500
mcr p15, 0, r1, c1, c1, 0
 
 
// Run main loop.
// Switch mode.
 
mrs r2, cpsr
// Program VIC to allow timer interrupts.
bic r2, r2, #31
ldr r0, =#0xFFFFFFA0    // VIC base address.
orr r2, r2, #16
add r0, r0, #4          // Move to INT_MASK
msr cpsr_c, r2
ldr r1, =#0x0           // Prepare mask value
 
str r1, [r0]            // Unmask all interrupt sources.
.set USR_SP_VALUE, 4000
 
ldr sp,=USR_SP_VALUE
// Program timer peripheral to tick every 32 clock cycles.
 
ldr r0 ,=#0xFFFFFFC0    // Timer base address.
// Run main loop.
ldr r1 ,=#1
 
str r1, [r0]            // Enable timer
// Program VIC to allow timer interrupts.
add r0, r0, #4
ldr r0, =VIC_BASE_ADDRESS // VIC base address.
ldr r1, =#32
add r0, r0, #4            // Move to INT_MASK
str r1, [r0]            // Program to 255 clocks.
mov r1, #0                // Prepare mask value
add r0, r0, #8
str r1, [r0]              // Unmask all interrupt sources.
ldr r1, =#0x1
 
str r1, [r0]            // Start the timer.
// Program timer peripheral to tick every 32 clock cycles.
 
ldr r0 ,=TIMER_BASE_ADDRESS     // Timer base address.
 
mov r1 , #1
 
str r1, [r0]                    // Enable timer
 
add r0, r0, #4
 
mov r1, #32
 
str r1, [r0]                    // Program to 255 clocks.
 
add r0, r0, #8
 
mov r1, #0x1
 
str r1, [r0]                    // Start the timer.
 
 
 
// Call C code
 
bl main
 
 
bl main
// Do SWI 0x0
swi #0x00
swi #0x00
here: b here
 
 
 
 
// Loop forever
 
here: b here
 
 
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