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# The Zip CPU
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# The Zip CPU
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The Zip CPU is a small, light-weight, RISC CPU. Specific design goals include:
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The Zip CPU is a small, light-weight, RISC CPU. Specific design goals include:
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- 32-bit. All registers, addresses, and instructions are 32-bits in length. While the byte-size itself was at one time 32-bits, the CPU now handles 8-bit bytes like all other CPUs
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- 32-bit. All registers, addresses, and instructions are 32-bits in length. While the byte-size itself was at one time 32-bits, the CPU now handles 8-bit bytes like all other CPUs
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- A RISC CPU. The ZipCPU does not implement any microcode for executing instructions. Instructions nominally complete in one cycle each, with exceptions for multiplies, divides, memory accesses, and (sometime) floating point instructions.
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- A RISC CPU. Instructions nominally complete in one cycle each, with exceptions for multiplies, divides, memory accesses, and (eventually) floating point instructions.
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- A load/store architecture. Only load and store instructions may access memory.
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- A load/store architecture. Only load and store instructions may access memory.
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- Wishbone compliant. All memory and peripherals are accessed across a single wishbone bus.
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- Wishbone compliant. All memory and peripherals are accessed across a single wishbone bus.
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- A Von-Neumann architecture, meaning that both instructions and data share a common bus.
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- A Von-Neumann architecture, meaning that both instructions and data share a common bus.
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- A pipelined architecture, having stages for prefetch, decode, read-operand(s), a combined stage containing the ALU, memory, divide, and floating point units, and then the final write-back stage.
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- A pipelined architecture, having stages for prefetch, decode, read-operand(s), a combined stage containing the ALU, memory, divide, and floating point units, and then the final write-back stage.
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- A two mode machine: supervisor and user, with each mode having a different access level.
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- A two mode machine: supervisor and user, with each mode having a different access level.
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- Completely open source, licensed under the GPL.
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- Completely open source, licensed under the GPL.
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## Unique features and characteristics
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## Unique features and characteristics
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- Only 29 instructions are currently implemented. Six additional instructions have been reserved for a floating point unit, but such a unit has yet to be implemented.
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- Only 29 instructions are currently implemented. Six additional instructions have been reserved for a floating point unit, but such a unit has yet to be implemented.
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- (Almost) all instructions can be executed conditionally. Exceptions include load immediate, the debug break instruction, the bus lock and simulation instructions, and the no-operation instruction.
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- (Almost) all instructions can be executed conditionally. Exceptions include load immediate, the debug break instruction, the bus lock and simulation instructions, and the no-operation instruction. The assembler will quietly turn a conditional load immediate into a two-instruction equivalent.
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- Simplfied wishbone bus. While the ZipCPU conforms to the Wishbone B4 standard, some simplifications have been made. All tgx lines have been removed, although the select lines have been kept. All accesses are (or can be) pipelined. Finally, the ZipCPU project (and its daughter projects/[peripherals](rtl/peripherals) assumes that the strobe line is zero whenever the cycle is zero. This simplifies peripheral processing.
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- Simplfied wishbone bus. While the ZipCPU conforms to the Wishbone B4 standard, some simplifications have been made. All tgx lines have been removed, although the select lines have been kept. All accesses are (or can be) pipelined. Finally, the ZipCPU project (and its daughter projects/[peripherals](rtl/peripherals)) assumes that the strobe line is zero whenever the cycle is zero. This simplifies peripheral processing.
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- The CPU makes heavy use of pipelined wishbone processing wherever and whenever it can. Hence, loading two vaues in a row may cost only one clock more than just loading the one value.
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- The CPU makes heavy use of pipelined wishbone processing wherever and whenever it can. Hence, loading two vaues in a row may cost only one clock more than just loading the one value.
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- The CPU has no interrupt vectors, but rather two register sets. On any interrupt, the CPU just switches from the user register set to the supervisor register set. This simplifies interrupt handling, since the CPU automatically saves, preserves, and restores the supervisor's context between enabling interrupts and receiving the next interrupt. An [interrupt peripheral](rtl/peripherals/icontrol.v) handles the combining of multiple interrupts into a single interrupt line.
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- The CPU has no interrupt vectors, but rather two register sets. On any interrupt, the CPU just switches from the user register set to the supervisor register set. This simplifies interrupt handling, since the CPU automatically saves, preserves, and restores the supervisor's context between enabling interrupts and receiving the next interrupt. An [interrupt peripheral](rtl/peripherals/icontrol.v) handles the combining of multiple interrupts into a single interrupt line.
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## Getting Started
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If you'd like to get started with the ZipCPU, you might wish to know that this
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repository contains the [CPU](./rtl/core/zipcpu.v), its [documentation](./doc/spec.pdf), and the [toolchain](./sw).
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The CPU implementation found here, though, is just that: a CPU. This
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implementation requires a bus with peripherals hanging off of it, things such
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as [RAM](https://github.com/ZipCPU/zbasic/blob/master/rtl/memdev.v),
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[flash (ROM)](https://github.com/ZipCPU/zbasic/blob/master/rtl/wbqspiflash.v),
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[serial port](https://github.com/ZipCPU/wbuart32), etc. This is just where
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I keep the CPU apart from any necessary peripherals.
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So, if you want to try out the CPU, feel free to download and build this
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repository (use `git-clone` with a depth of 1--there's a lot of stuff in the
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git repo that you don't necessarily need). You'll need it for the binutils,
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GCC, and [newlib](https://sourceware.org/newlib) support provided by it.
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Once you've built these tools, then I'd suggest you look into the
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[ZBasic repository](https://github.com/ZipCPU/zbasic). That repository places
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the CPU in an environment with
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[block RAM](https://github.com/ZipCPU/zbasic/blob/master/rtl/memdev.v),
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[QSPI flash](https://github.com/ZipCPU/zbasic/blob/master/rtl/wbqspiflash.v),
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and [SD-card (SPI protocol)](https://github.com/ZipCPU/sdspi) access. From
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that repository, you can either tweak the distro
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([main.v](https://github.com/ZipCPU/zbasic/blob/master/rtl/main.v),
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[regdefs.h](https://github.com/ZipCPU/zbasic/blob/master/sw/host/regdefs.h),
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[board.h](https://github.com/ZipCPU/zbasic/blob/master/sw/zlib/board.h),
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[board.ld](https://github.com/ZipCPU/zbasic/blob/master/sw/board/board.ld)) to
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add the peripherals you want to use the CPU with, or you can use
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[autofpga](https://github.com/ZipCPU/autofpga)
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to adjust your RAM size, add or remove peripherals and so forth while
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maintaining (creating, really) all of these files for you.
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Even more than that,
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the [ZBasic distribution](https://github.com/ZipCPU/zbasic) has complete
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[Verilator support](https://github.com/ZipCPU/zbasic/tree/sim/verilator)
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so that you can build your design, and simulate it, from
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power on reset through bootloader through ... well, however far you'd like to
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simulate and your disk has space for.
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If you aren't interested in simulating the CPU, there is an assembly level
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[debugger](https://github.com/ZipCPU/zbasic/blob/master/sw/host/zipdbg.cpp)
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that you can use to stop and step the CPU, as well as an
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integrated [wishbone scope](https://github.com/ZipCPU/wbscope) that
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you can use to get traces from within the design while it is running.
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## Need help?
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If you'd like to use the ZipCPU, and don't know where to begin, feel free
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to find me on IRC as ZipCPU. I tend to inhabit the #openarty channel
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of the Freenode IRC server. If you get stuck, I've been known to help folks
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out there as well.
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## Current Status
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## Current Status
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20170309: The CPU has just been updated for 8-bit byte support. Several additional changes include:
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I've recently blogged about the ZipCPU at [zipcpu.com](http://zipcpu.com)!
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- The CPU has been rebuilt to add four new instructions, LB (load byte), SB (store byte), LH (load half-word or short), and SH (store half-word or short).
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Articles you might find valuable include:
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- The LOD/STO instructions have been renamed LW (load word) and SW (store word) respectively.
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- The CPU is now also, as a result, completely big--endian, which it only sort of was before.
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- [An overview of the ZipCPU's ISA](http://zipcpu.com/zipcpu/2018/01/01/zipcpu-isa.html)
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- The maximum wishbone bus address width of the CPU is no longer 32-bits, where each address references a 32-bit number, but rather 30-bits. The final two bits are used to determine the values of the (new) select lines. This means that the ZipCPU now suffers from the same 4GB memory limit as all other 32-bit CPUs.
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- [How-to build the tool-chain, and test the CPU](http://zipcpu.com/zipcpu/2018/01/31/cpu-build.html)
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- The instruction set has been reordered--programs written for the 32-bit byte master branch will not work on this 8-bit byte branch.
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- [Formal properties of a WB bus](http://zipcpu.com/zipcpu/2017/11/07/wb-formal.html)
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- The greater than (GT) condition has been replaced by a not-carry (NC) condition, in order to simplify what the compiler needs to do for unsigned numbers.
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- [Formally proving the prefetch](http://zipcpu.com/zipcpu/2017/11/18/prefetch.html)
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- The machine ID in the ZipCPU ELF/object files has been changed from 0xdadd to 0xdad1, to reflect this change. (This is an unregistered ID, so ... there _may_ be other computers out there with this ELF ID ...)
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- The ZipCPU supports several new simulation support or SIM instructions. These can be used to write messages to the simulator console if desired.
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I'm also working on [formally verifying the entire
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- There are now two simulators for the ZipCPU: A [C++ simulator](sim/cpp) that is independent of the Verilog, and a [Verilator](https://www.veripool.org/wiki/verilator) based [simulator](sim/verilated) that exercises the CPUs core logic.
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CPU](http://zipcpu.com/blog/2018/01/22/formal-progress.html). My goal will be
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- The two simulators are designed to closely match the performance of a bare-bones [basic ZipCPU system](https://github.com/ZipCPU/zbasic). Further, the newlib library as built is designed to support this minimum ZipCPU implementation.
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to [prove, via
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- The Assembler now implements the Compressed Instruction Set (CIS) by default when it can. (This instruction set was formerly and inappropriately named the VLIW instruction set. It has since been redesigned.) Instruction words using this format can pack two instructions into a single instruction word.
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yosys-smtbmc](http://zipcpu.com/blog/2017/10/19/formal-intro.html), that the
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ZipCPU will never enter into an invalid state. I've been successful so far
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proving the various components of the ZipCPU. What remains is the CPU
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itself.
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Unlike the ZipCPU before these changes, newlib now compiles and appears to work with the ZipCPU (without floating point support).
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Also, unlike before, the ZipCPU is now small enough to be able to include a divide unit, and a double-fetch (uses pipelined WB for one word) when build for the Spartan-6/LX4.
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## Not yet integrated
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## Not yet integrated
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- An [MMU](rtl/peripherals/zipmmu.v) has been written for the ZipCPU, but not yet integrated into it
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- An [MMU](rtl/peripherals/zipmmu.v) has been written for the ZipCPU, and even
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- Likewise, a [data cache](../../tree/master/rtl/core/dcache.v) has been written for the ZipCPU, but not yet integrated into it
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integrated into it, but it has not yet been tested. Using
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- I would also like to integrate [SDCard support](https://github.com/ZipCPU/sdspi) into the newlib C-library to give the CPU file access
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[formal methods](http://zipcpu.com/blog/2017/10/19/formal-intro.html),
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- The [ZipOS](https://github.com/ZipCPU/s6soc/tree/master/sw/zipos) would greatly speed up and improve the bare bones newlib library.
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I've now proved that this component works. A
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[test bench](sim/verilator/zipmmu_tb.cpp) also exists
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to exercise it.
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- A [data cache](../../tree/master/rtl/core/dcache.v) has been
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written for the ZipCPU, but has yet to be fully optimized.
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- I would also like to integrate [SDCard
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support](https://github.com/ZipCPU/sdspi) into the
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[newlib](https://sourceware.org/newlib) C-library to give
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the CPU file access. If and when this takes place, it will take place as
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part of the [ZBasic repository](https://github.com/ZipCPU/zbasic) first.
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- The [ZipOS](https://github.com/ZipCPU/s6soc/tree/master/sw/zipos)
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would greatly speed up and improve the bare bones [newlib](https://sourceware.org/newlib) library--primarily
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by providing "O/S" level interrupt support when using the library. This
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integration has not (yet) been accomplished.
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On the other hand, if the [MMU](rtl/peripherals/zipmmu.v) is available,
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I might rather just create a Linux distribution.
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## Commercial Opportunities
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## Commercial Opportunities
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If the GPLv3 license is insufficient for your needs, other licenses (for all but
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If the [GPLv3 license](https://www.gnu.org/licenses/gpl-3.0.en.html) is
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the tool-chain) can be purchased from Gisselquist Technology, LLC.
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insufficient for your needs, other licenses (for all but the tool-chain) can
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be purchased from Gisselquist Technology, LLC.
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