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[/] [zipcpu/] [trunk/] [bench/] [asm/] [zipdhry.S] - Diff between revs 86 and 152

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Rev 86 Rev 152
Line 48... Line 48...
//      DMIPS:          38.0    100 MHz (sim)   0.38    // 20151211 (new ISA)
//      DMIPS:          38.0    100 MHz (sim)   0.38    // 20151211 (new ISA)
//      DMIPS:          40.5    100 MHz (sim)   0.41    // 20151212 (H/W DIV)
//      DMIPS:          40.5    100 MHz (sim)   0.41    // 20151212 (H/W DIV)
//      DMIPS:           8.2    100 MHz (sim)   0.08    // 20151104--!pipelined
//      DMIPS:           8.2    100 MHz (sim)   0.08    // 20151104--!pipelined
//      DMIPS:          60.1    100 MHz (sim)   0.60    // 20151215 (New PF)
//      DMIPS:          60.1    100 MHz (sim)   0.60    // 20151215 (New PF)
//      DMIPS:          60.0    100 MHz (sim)   0.60    // 20151226 (BugFix)
//      DMIPS:          60.0    100 MHz (sim)   0.60    // 20151226 (BugFix)
 
//      DMIPS:                  100 MHz (sim)   0.67    // 20160406 (??)
 
//      DMIPS:                  100 MHz (sim)   0.58    // 20160409 (BugFix)
// On real hardware:
// On real hardware:
//      DMIPS:          24.7    100 MHz (basys) 0.25    // Initial baseline
//      DMIPS:          24.7    100 MHz (basys) 0.25    // Initial baseline
//      DMIPS:          30.6    100 MHz (basys) 0.31    // 20151017
//      DMIPS:          30.6    100 MHz (basys) 0.31    // 20151017
//      DMIPS:          48.4    100 MHz (basys) 0.48    // 20151227 (New pf/ISA)
//      DMIPS:          48.4    100 MHz (basys) 0.48    // 20151227 (New pf/ISA)
//
//
Line 837... Line 839...
        ADD     R2,R5
        ADD     R2,R5
        STO     R3,(R5)
        STO     R3,(R5)
        STO     R3,1(R5)
        STO     R3,1(R5)
        STO     R2,30(R5)
        STO     R2,30(R5)
        MOV     R2,R5
        MOV     R2,R5
        MPYU    50,R5   ; R5 = 50 * R2 = 50 * loc
        MPY     50,R5   ; R5 = 50 * R2 = 50 * loc
        ADD     R1,R5   ; R5 = &b[loc][0]
        ADD     R1,R5   ; R5 = &b[loc][0]
        MOV     R5,R6   ; R6 = &b[loc][0]
        MOV     R5,R6   ; R6 = &b[loc][0]
        ADD     R2,R5   ; R5 = &b[loc][loc]
        ADD     R2,R5   ; R5 = &b[loc][loc]
        MOV     R2,R4   ; R4 = loc = index
        MOV     R2,R4   ; R4 = loc = index
proc_8_top_of_loop:
proc_8_top_of_loop:
Line 1380... Line 1382...
        CMP     R6,R5
        CMP     R6,R5
        BGE     dhrystone_end_while_loop
        BGE     dhrystone_end_while_loop
dhrystone_while_loop:
dhrystone_while_loop:
//                      lcl_int_3 = 5 * lcl_int_1 - lcl_int_2;
//                      lcl_int_3 = 5 * lcl_int_1 - lcl_int_2;
        MOV     R5,R7
        MOV     R5,R7
        LDI     5,R0
        MPY     5,R7
        MPYS    R0,R7
 
        SUB     R6,R7
        SUB     R6,R7
        STO     R7,lcl_int_3(SP)
        STO     R7,lcl_int_3(SP)
#ifndef SKIP_SHORT_CIRCUITS
#ifndef SKIP_SHORT_CIRCUITS
        CMP     7,R7
        CMP     7,R7
        BUSY.NZ
        BUSY.NZ
Line 1503... Line 1504...
        BUSY.NZ
        BUSY.NZ
#endif
#endif
//
//
//              lcl_int_2 = lcl_int_2 * lcl_int_1;
//              lcl_int_2 = lcl_int_2 * lcl_int_1;
        LOD     lcl_int_1(SP),R5
        LOD     lcl_int_1(SP),R5
        MPYS    R5,R6   ; lcl_int_2 =
        MPY     R5,R6   ; lcl_int_2 =
//              lcl_int_1 = lcl_int_2 / lcl_int_3;
//              lcl_int_1 = lcl_int_2 / lcl_int_3;
#ifdef  HARDWARE_DIVIDE
#ifdef  HARDWARE_DIVIDE
        LOD     lcl_int_3(SP),R1
        LOD     lcl_int_3(SP),R1
        MOV     R6,R0
        MOV     R6,R0
        DIVS    R1,R0
        DIVS    R1,R0
Line 1523... Line 1524...
#endif
#endif
        STO     R0,lcl_int_1(SP)        ;;; TODO FAILS HERE (Watched it fail!)
        STO     R0,lcl_int_1(SP)        ;;; TODO FAILS HERE (Watched it fail!)
//              lcl_int_2 = 7 * ( lcl_int_2 - lcl_int_3) - lcl_int_1;
//              lcl_int_2 = 7 * ( lcl_int_2 - lcl_int_3) - lcl_int_1;
        LOD     lcl_int_3(SP),R2
        LOD     lcl_int_3(SP),R2
        SUB     R2,R6
        SUB     R2,R6
        MPYS    7,R6
        MPY     7,R6
        SUB     R0,R6
        SUB     R0,R6
//              proc_2(&lcl_int_1);
//              proc_2(&lcl_int_1);
#ifndef SKIP_SHORT_CIRCUITS
#ifndef SKIP_SHORT_CIRCUITS
        LOD     lcl_int_1(SP),R0
        LOD     lcl_int_1(SP),R0
        CMP     1,R0
        CMP     1,R0

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