////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: memsim.cpp
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// Filename: memsim.cpp
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//
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU core
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// Project: Zip CPU -- a small, lightweight, RISC CPU core
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//
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//
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// Purpose: This creates a memory like device to act on a WISHBONE bus.
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// Purpose: This creates a memory like device to act on a WISHBONE bus.
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// It doesn't exercise the bus thoroughly, but does give some
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// It doesn't exercise the bus thoroughly, but does give some
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// exercise to the bus to see whether or not the bus master
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// exercise to the bus to see whether or not the bus master
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// can control it.
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// can control it.
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Tecnology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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#include <stdio.h>
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#include <stdio.h>
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#include <assert.h>
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#include <assert.h>
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#include "memsim.h"
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#include "memsim.h"
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MEMSIM::MEMSIM(const unsigned int nwords) {
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MEMSIM::MEMSIM(const unsigned int nwords) {
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unsigned int nxt;
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unsigned int nxt;
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for(nxt=1; nxt < nwords; nxt<<=1)
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for(nxt=1; nxt < nwords; nxt<<=1)
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;
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;
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m_len = nxt; m_mask = nxt-1;
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m_len = nxt; m_mask = nxt-1;
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m_mem = new BUSW[m_len];
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m_mem = new BUSW[m_len];
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}
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}
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MEMSIM::~MEMSIM(void) {
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MEMSIM::~MEMSIM(void) {
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delete[] m_mem;
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delete[] m_mem;
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}
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}
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void MEMSIM::load(const char *fname) {
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void MEMSIM::load(const char *fname) {
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FILE *fp;
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FILE *fp;
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unsigned int nr;
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unsigned int nr;
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fp = fopen(fname, "r");
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fp = fopen(fname, "r");
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if (!fp) {
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if (!fp) {
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fprintf(stderr, "Could not open/load file \'%s\'\n",
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fprintf(stderr, "Could not open/load file \'%s\'\n",
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fname);
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fname);
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perror("O/S Err:");
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perror("O/S Err:");
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fprintf(stderr, "\tInitializing memory with zero instead.\n");
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fprintf(stderr, "\tInitializing memory with zero instead.\n");
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nr = 0;
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nr = 0;
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} else {
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} else {
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nr = fread(m_mem, sizeof(BUSW), m_len, fp);
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nr = fread(m_mem, sizeof(BUSW), m_len, fp);
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fclose(fp);
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fclose(fp);
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if (nr != m_len) {
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if (nr != m_len) {
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fprintf(stderr, "Only read %d of %d words\n",
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fprintf(stderr, "Only read %d of %d words\n",
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nr, m_len);
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nr, m_len);
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fprintf(stderr, "\tFilling the rest with zero.\n");
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fprintf(stderr, "\tFilling the rest with zero.\n");
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}
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}
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}
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}
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for(; nr<m_len; nr++)
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for(; nr<m_len; nr++)
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m_mem[nr] = 0l;
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m_mem[nr] = 0l;
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}
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}
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void MEMSIM::apply(const unsigned int clk, const unsigned char wb_cyc,
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void MEMSIM::apply(const unsigned int clk, const unsigned char wb_cyc,
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const unsigned char wb_stb, const unsigned char wb_we,
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const unsigned char wb_stb, const unsigned char wb_we,
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const BUSW wb_addr, const BUSW wb_data,
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const BUSW wb_addr, const BUSW wb_data,
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unsigned char &o_ack, unsigned char &o_stall, BUSW &o_data) {
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unsigned char &o_ack, unsigned char &o_stall, BUSW &o_data) {
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if ((wb_cyc)&&(wb_stb)&&(clk)) {
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if ((wb_cyc)&&(wb_stb)&&(clk)) {
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if (wb_we)
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if (wb_we)
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m_mem[wb_addr & m_mask] = wb_data;
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m_mem[wb_addr & m_mask] = wb_data;
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o_ack = 1;
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o_ack = 1;
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o_stall= 0;
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o_stall= 0;
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o_data = m_mem[wb_addr & m_mask];
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o_data = m_mem[wb_addr & m_mask];
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/*
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/*
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printf("MEMBUS -- ACK %s 0x%08x - 0x%08x\n",
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printf("MEMBUS -- ACK %s 0x%08x - 0x%08x\n",
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(wb_we)?"WRITE":"READ",
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(wb_we)?"WRITE":"READ",
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wb_addr, o_data);
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wb_addr, o_data);
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*/
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*/
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} else if (clk) {
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} else if (clk) {
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o_ack = 0;
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o_ack = 0;
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o_stall = 0;
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o_stall = 0;
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}
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}
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}
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}
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