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[/] [zipcpu/] [trunk/] [bench/] [cpp/] [memsim.h] - Diff between revs 69 and 197

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////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Filename:    memsim.h
// Filename:    memsim.h
//
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU core
// Project:     Zip CPU -- a small, lightweight, RISC CPU core
//
//
// Purpose:     This creates a memory like device to act on a WISHBONE bus.
// Purpose:     This creates a memory like device to act on a WISHBONE bus.
//              It doesn't exercise the bus thoroughly, but does give some
//              It doesn't exercise the bus thoroughly, but does give some
//              exercise to the bus to see whether or not the bus master
//              exercise to the bus to see whether or not the bus master
//              can control it.
//              can control it.
//
//
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
//
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
// for more details.
//
//
// You should have received a copy of the GNU General Public License along
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.)  If not, see
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
// <http://www.gnu.org/licenses/> for a copy.
//
//
// License:     GPL, v3, as defined and found on www.gnu.org,
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//              http://www.gnu.org/licenses/gpl.html
//
//
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
#ifndef MEMSIM_H
#ifndef MEMSIM_H
#define MEMSIM_H
#define MEMSIM_H
 
 
class   MEMSIM {
class   MEMSIM {
public:
public:
        typedef unsigned int    BUSW;
        typedef unsigned int    BUSW;
        typedef unsigned char   uchar;
        typedef unsigned char   uchar;
 
 
        BUSW    *m_mem, m_len, m_mask;
        BUSW    *m_mem, m_len, m_mask;
 
        int     m_nxt_ack;
 
        BUSW    m_nxt_data;
 
 
 
 
        MEMSIM(const unsigned int nwords);
        MEMSIM(const unsigned int nwords);
        ~MEMSIM(void);
        ~MEMSIM(void);
        void    load(const char *fname);
        void    load(const char *fname);
        void    apply(const unsigned clk, const uchar wb_cyc, const uchar wb_stb,
        void    apply(const unsigned clk, const uchar wb_cyc, const uchar wb_stb,
                                const uchar wb_we,
                                const uchar wb_we,
                        const BUSW wb_addr, const BUSW wb_data,
                        const BUSW wb_addr, const BUSW wb_data,
                        uchar &o_ack, uchar &o_stall, BUSW &o_data);
                        uchar &o_ack, uchar &o_stall, BUSW &o_data);
        void    operator()(const unsigned clk, const uchar wb_cyc, const uchar wb_stb, const uchar wb_we,
        void    operator()(const unsigned clk, const uchar wb_cyc, const uchar wb_stb, const uchar wb_we,
                        const BUSW wb_addr, const BUSW wb_data,
                        const BUSW wb_addr, const BUSW wb_data,
                        uchar &o_ack, uchar &o_stall, BUSW &o_data) {
                        uchar &o_ack, uchar &o_stall, BUSW &o_data) {
                apply(clk, wb_cyc, wb_stb, wb_we, wb_addr, wb_data, o_ack, o_stall, o_data);
                apply(clk, wb_cyc, wb_stb, wb_we, wb_addr, wb_data, o_ack, o_stall, o_data);
        }
        }
        BUSW &operator[](const BUSW addr) { return m_mem[addr&m_mask]; }
        BUSW &operator[](const BUSW addr) { return m_mem[addr&m_mask]; }
};
};
 
 
#endif
#endif
 
 

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