OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [bench/] [cpp/] [zippy_tb.cpp] - Diff between revs 155 and 187

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 155 Rev 187
Line 13... Line 13...
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
Line 97... Line 97...
                m_last_pc_valid = true;
                m_last_pc_valid = true;
                m_last_pc = m_pc;
                m_last_pc = m_pc;
        }
        }
};
};
 
 
 
extern  FILE    *gbl_dbgfp;
 
FILE    *gbl_dbgfp = NULL;
 
 
// No particular "parameters" need definition or redefinition here.
// No particular "parameters" need definition or redefinition here.
class   ZIPPY_TB : public TESTB<Vzipsystem> {
class   ZIPPY_TB : public TESTB<Vzipsystem> {
public:
public:
        unsigned long   m_mem_size;
        unsigned long   m_mem_size;
Line 114... Line 116...
 
 
        ZIPPY_TB(void) : m_mem_size(MEMWORDS), m_mem(m_mem_size) {
        ZIPPY_TB(void) : m_mem_size(MEMWORDS), m_mem(m_mem_size) {
                if (false) {
                if (false) {
                        m_dbgfp = fopen("dbg.txt", "w");
                        m_dbgfp = fopen("dbg.txt", "w");
                        dbg_flag = true;
                        dbg_flag = true;
 
                        gbl_dbgfp = m_dbgfp;
                } else {
                } else {
                        m_dbgfp = NULL;
                        m_dbgfp = NULL;
                        dbg_flag = false;
                        dbg_flag = false;
 
                        gbl_dbgfp = NULL;
                }
                }
                bomb = false;
                bomb = false;
                m_cursor = 0;
                m_cursor = 0;
                m_show_user_timers = false;
                m_show_user_timers = false;
 
 
Line 477... Line 481...
                mvprintw(ln,60,"%s",
                mvprintw(ln,60,"%s",
                        (m_core->v__DOT__thecpu__DOT__wr_reg_id == 0x0e)
                        (m_core->v__DOT__thecpu__DOT__wr_reg_id == 0x0e)
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce)
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce)
                                ?"V"
                                ?"V"
                        :(((m_core->v__DOT__thecpu__DOT__wr_flags_ce)
                        :(((m_core->v__DOT__thecpu__DOT__wr_flags_ce)
                                &&(!m_core->v__DOT__thecpu__DOT__alu_gie))?"+"
                                &&(!m_core->v__DOT__thecpu__DOT__r_alu_gie))?"+"
                        :" "));
                        :" "));
                ln++;
                ln++;
 
 
                if (m_core->v__DOT__thecpu__DOT__gie)
                if (m_core->v__DOT__thecpu__DOT__gie)
                        attron(A_BOLD);
                        attron(A_BOLD);
Line 491... Line 495...
                mvprintw(ln, 42, "DCDR=%02x %s%s",
                mvprintw(ln, 42, "DCDR=%02x %s%s",
                        dcdR(),
                        dcdR(),
                        (m_core->v__DOT__thecpu__DOT__dcdR_wr)?"W":" ",
                        (m_core->v__DOT__thecpu__DOT__dcdR_wr)?"W":" ",
                        (m_core->v__DOT__thecpu__DOT__dcdF_wr)?"F":" ");
                        (m_core->v__DOT__thecpu__DOT__dcdF_wr)?"F":" ");
                mvprintw(ln, 62, "OPR =%02x %s%s",
                mvprintw(ln, 62, "OPR =%02x %s%s",
                        m_core->v__DOT__thecpu__DOT__opR,
                        m_core->v__DOT__thecpu__DOT__r_opR,
                        (m_core->v__DOT__thecpu__DOT__opR_wr)?"W":" ",
                        (m_core->v__DOT__thecpu__DOT__opR_wr)?"W":" ",
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"F":" ");
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"F":" ");
                ln++;
                ln++;
                showreg(ln, 0, "uR0 ", 16, (m_cursor==28));
                showreg(ln, 0, "uR0 ", 16, (m_cursor==28));
                showreg(ln,20, "uR1 ", 17, (m_cursor==29));
                showreg(ln,20, "uR1 ", 17, (m_cursor==29));
Line 538... Line 542...
                mvprintw(ln,60,"%s",
                mvprintw(ln,60,"%s",
                        (m_core->v__DOT__thecpu__DOT__wr_reg_id == 0x1e)
                        (m_core->v__DOT__thecpu__DOT__wr_reg_id == 0x1e)
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce)
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce)
                                ?"V"
                                ?"V"
                        :(((m_core->v__DOT__thecpu__DOT__wr_flags_ce)
                        :(((m_core->v__DOT__thecpu__DOT__wr_flags_ce)
                                &&(m_core->v__DOT__thecpu__DOT__alu_gie))?"+"
                                &&(m_core->v__DOT__thecpu__DOT__r_alu_gie))?"+"
                        :" "));
                        :" "));
 
 
                attroff(A_BOLD);
                attroff(A_BOLD);
                ln+=1;
                ln+=1;
 
 
Line 561... Line 565...
 
 
                mvprintw(ln, 0, "PFCACH: v=%08x, %s%s, tag=%08x, pf_pc=%08x, lastpc=%08x",
                mvprintw(ln, 0, "PFCACH: v=%08x, %s%s, tag=%08x, pf_pc=%08x, lastpc=%08x",
                        m_core->v__DOT__thecpu__DOT__pf__DOT__vmask,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__vmask,
                        (m_core->v__DOT__thecpu__DOT__pf__DOT__r_v)?"V":" ",
                        (m_core->v__DOT__thecpu__DOT__pf__DOT__r_v)?"V":" ",
                        (m_core->v__DOT__thecpu__DOT__pf_illegal)?"I":" ",
                        (m_core->v__DOT__thecpu__DOT__pf_illegal)?"I":" ",
                        m_core->v__DOT__thecpu__DOT__pf__DOT__tagval,
                        (m_core->v__DOT__thecpu__DOT__pf__DOT__tagsrc)
 
                        ?(m_core->v__DOT__thecpu__DOT__pf__DOT__tagvalipc)
 
                        :(m_core->v__DOT__thecpu__DOT__pf__DOT__tagvallst),
                        m_core->v__DOT__thecpu__DOT__pf_pc,
                        m_core->v__DOT__thecpu__DOT__pf_pc,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__lastpc);
                        m_core->v__DOT__thecpu__DOT__pf__DOT__lastpc);
 
 
                ln++;
                ln++;
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
Line 578... Line 584...
                        (pfstall())?"STL":"   ",
                        (pfstall())?"STL":"   ",
                        (m_core->v__DOT__wb_data)); ln++;
                        (m_core->v__DOT__wb_data)); ln++;
#endif
#endif
 
 
                mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
                mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
                        (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GCY"
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_gbl)?"GCY"
                                :((m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LCY":"   "),
                                :((m_core->v__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_lcl)?"LCY":"   "),
                        (m_core->v__DOT__thecpu__DOT__mem_stb_gbl)?"GSB"
                        (m_core->v__DOT__thecpu__DOT__mem_stb_gbl)?"GSB"
                                :((m_core->v__DOT__thecpu__DOT__mem_stb_lcl)?"LSB":"   "),
                                :((m_core->v__DOT__thecpu__DOT__mem_stb_lcl)?"LSB":"   "),
                        (m_core->v__DOT__thecpu__DOT__mem_we )?"WE":"  ",
                        (m_core->v__DOT__thecpu__DOT__mem_we )?"WE":"  ",
                        (m_core->v__DOT__thecpu__DOT__mem_addr),
                        (m_core->v__DOT__thecpu__DOT__mem_addr),
                        (m_core->v__DOT__thecpu__DOT__mem_data),
                        (m_core->v__DOT__thecpu__DOT__mem_data),
Line 615... Line 621...
#ifdef  OPT_PIPELINED_BUS_ACCESS
#ifdef  OPT_PIPELINED_BUS_ACCESS
                mvprintw(ln-1, 0, "Mem CE: %d = %d%d%d%d%d, stall: %d = %d%d(%d|%d%d|..)",
                mvprintw(ln-1, 0, "Mem CE: %d = %d%d%d%d%d, stall: %d = %d%d(%d|%d%d|..)",
                        (m_core->v__DOT__thecpu__DOT__mem_ce),
                        (m_core->v__DOT__thecpu__DOT__mem_ce),
                        (m_core->v__DOT__thecpu__DOT__master_ce),       //1
                        (m_core->v__DOT__thecpu__DOT__master_ce),       //1
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),     //0
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),     //0
                        (!m_core->v__DOT__thecpu__DOT__clear_pipeline), //1
                        (!m_core->v__DOT__thecpu__DOT__new_pc), //1
 
                        // (!m_core->v__DOT__thecpu__DOT__clear_pipeline),      //1
                        (m_core->v__DOT__thecpu__DOT__set_cond),        //1
                        (m_core->v__DOT__thecpu__DOT__set_cond),        //1
                        (!mem_stalled()),       //1
                        (!mem_stalled()),       //1
 
 
                        (mem_stalled()),
                        (mem_stalled()),
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),
Line 683... Line 690...
                        mvprintw(ln-1,10,"M");
                        mvprintw(ln-1,10,"M");
 
 
                showins(ln, "Op",
                showins(ln, "Op",
                        op_ce(),
                        op_ce(),
                        m_core->v__DOT__thecpu__DOT__opvalid,
                        m_core->v__DOT__thecpu__DOT__opvalid,
                        m_core->v__DOT__thecpu__DOT__op_gie,
                        m_core->v__DOT__thecpu__DOT__r_op_gie,
                        m_core->v__DOT__thecpu__DOT__op_stall,
                        m_core->v__DOT__thecpu__DOT__op_stall,
                        op_pc(),
                        op_pc(),
#ifdef  OPT_VLIW
#ifdef  OPT_VLIW
                        m_core->v__DOT__thecpu__DOT__r_op_phase
                        m_core->v__DOT__thecpu__DOT__r_op_phase
#else
#else
Line 706... Line 713...
 
 
                if (m_core->v__DOT__thecpu__DOT__opvalid_mem) {
                if (m_core->v__DOT__thecpu__DOT__opvalid_mem) {
                        showins(ln, "Mm",
                        showins(ln, "Mm",
                                m_core->v__DOT__thecpu__DOT__mem_ce,
                                m_core->v__DOT__thecpu__DOT__mem_ce,
                                m_core->v__DOT__thecpu__DOT__mem_pc_valid,
                                m_core->v__DOT__thecpu__DOT__mem_pc_valid,
                                m_core->v__DOT__thecpu__DOT__alu_gie,
                                m_core->v__DOT__thecpu__DOT__r_alu_gie,
#ifdef  OPT_PIPELINED
#ifdef  OPT_PIPELINED
                                m_core->v__DOT__thecpu__DOT__mem_stall,
                                m_core->v__DOT__thecpu__DOT__mem_stall,
#else
#else
                                0,
                                0,
#endif
#endif
Line 723... Line 730...
                        );
                        );
                } else {
                } else {
                        showins(ln, "Al",
                        showins(ln, "Al",
                                m_core->v__DOT__thecpu__DOT__alu_ce,
                                m_core->v__DOT__thecpu__DOT__alu_ce,
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
                                m_core->v__DOT__thecpu__DOT__alu_gie,
                                m_core->v__DOT__thecpu__DOT__r_alu_gie,
#ifdef  OPT_PIPELINED
#ifdef  OPT_PIPELINED
                                m_core->v__DOT__thecpu__DOT__alu_stall,
                                m_core->v__DOT__thecpu__DOT__alu_stall,
#else
#else
                                0,
                                0,
#endif
#endif
Line 751... Line 758...
#endif
#endif
                // else if (m_core->v__DOT__thecpu__DOT__alu_illegal_op)
                // else if (m_core->v__DOT__thecpu__DOT__alu_illegal_op)
                        // mvprintw(ln-1,10,"i");
                        // mvprintw(ln-1,10,"i");
 
 
                mvprintw(ln-5, 65,"%s %s",
                mvprintw(ln-5, 65,"%s %s",
                        (m_core->v__DOT__thecpu__DOT__op_break)?"OB":"  ",
                        (m_core->v__DOT__thecpu__DOT__r_op_break)?"OB":"  ",
                        (m_core->v__DOT__thecpu__DOT__clear_pipeline)?"CLRP":"    ");
                        (m_core->v__DOT__thecpu__DOT__new_pc)?"CLRP":"    ");
                mvprintw(ln-4, 48,
                mvprintw(ln-4, 48,
                        (m_core->v__DOT__thecpu__DOT__new_pc)?"new-pc":"      ");
                        (m_core->v__DOT__thecpu__DOT__new_pc)?"new-pc":"      ");
                printw("(%s:%02x,%x)",
                printw("(%s:%02x,%x)",
                        (m_core->v__DOT__thecpu__DOT__set_cond)?"SET":"   ",
                        (m_core->v__DOT__thecpu__DOT__set_cond)?"SET":"   ",
                        (m_core->v__DOT__thecpu__DOT__opF&0x0ff),
                        (m_core->v__DOT__thecpu__DOT__opF&0x0ff),
                        (m_core->v__DOT__thecpu__DOT__op_gie)
                        (m_core->v__DOT__thecpu__DOT__r_op_gie)
                                ?  (m_core->v__DOT__thecpu__DOT__w_uflags)
                                ?  (m_core->v__DOT__thecpu__DOT__w_uflags)
                                : (m_core->v__DOT__thecpu__DOT__w_iflags));
                                : (m_core->v__DOT__thecpu__DOT__w_iflags));
 
 
                printw("(%s%s%s:%02x)",
                printw("(%s%s%s:%02x)",
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"OF":"  ",
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"OF":"  ",
Line 774... Line 781...
                        m_core->v__DOT__thecpu__DOT__dcdI);
                        m_core->v__DOT__thecpu__DOT__dcdI);
                mvprintw(ln-2, 48, "r_opB: 0x%08x",
                mvprintw(ln-2, 48, "r_opB: 0x%08x",
                        m_core->v__DOT__thecpu__DOT__opB);
                        m_core->v__DOT__thecpu__DOT__opB);
                */
                */
                mvprintw(ln-3, 48, "Op(%x)%8x,%8x->",
                mvprintw(ln-3, 48, "Op(%x)%8x,%8x->",
                        m_core->v__DOT__thecpu__DOT__opn,
                        m_core->v__DOT__thecpu__DOT__r_opn,
                        m_core->v__DOT__thecpu__DOT__opA,
                        m_core->v__DOT__thecpu__DOT__opA,
                        m_core->v__DOT__thecpu__DOT__opB);
                        m_core->v__DOT__thecpu__DOT__opB);
                if (m_core->v__DOT__thecpu__DOT__alu_valid)
                if (m_core->v__DOT__thecpu__DOT__alu_valid)
                        printw("%08x", m_core->v__DOT__thecpu__DOT__alu_result);
                        printw("%08x", m_core->v__DOT__thecpu__DOT__alu_result);
                else
                else
Line 814... Line 821...
                        errcount++;
                        errcount++;
                if (errcount >= MAXERR) {
                if (errcount >= MAXERR) {
                        endwin();
                        endwin();
 
 
                        printf("ERR: errcount >= MAXERR on wb_read(a=%x)\n", a);
                        printf("ERR: errcount >= MAXERR on wb_read(a=%x)\n", a);
                        printf("Clear-Pipeline = %d\n", m_core->v__DOT__thecpu__DOT__clear_pipeline);
                        // printf("Clear-Pipeline = %d\n", m_core->v__DOT__thecpu__DOT__clear_pipeline);
                        printf("cpu-dbg-stall  = %d\n", m_core->v__DOT__cpu_dbg_stall);
                        printf("cpu-dbg-stall  = %d\n", m_core->v__DOT__thecpu__DOT__r_halted);
                        printf("pf_cyc         = %d\n", m_core->v__DOT__thecpu__DOT__pf_cyc);
                        printf("pf_cyc         = %d\n", m_core->v__DOT__thecpu__DOT__pf_cyc);
                        printf("mem_cyc_gbl    = %d\n", m_core->v__DOT__thecpu__DOT__mem_cyc_gbl);
                        printf("mem_cyc_gbl    = %d\n", (m_core->v__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_gbl));
                        printf("mem_cyc_lcl    = %d\n", m_core->v__DOT__thecpu__DOT__mem_cyc_lcl);
                        printf("mem_cyc_lcl    = %d\n", m_core->v__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_lcl);
                        printf("opvalid        = %d\n", m_core->v__DOT__thecpu__DOT__opvalid);
                        printf("opvalid        = %d\n", m_core->v__DOT__thecpu__DOT__opvalid);
                        printf("dcdvalid       = %d\n", dcdvalid()?1:0);
                        printf("dcdvalid       = %d\n", dcdvalid()?1:0);
                        printf("dcd_ce         = %d\n", dcd_ce()?1:0);
                        printf("dcd_ce         = %d\n", dcd_ce()?1:0);
#ifdef  OPT_PIPELINED
#ifdef  OPT_PIPELINED
                        printf("dcd_stalled    = %d\n", m_core->v__DOT__thecpu__DOT__dcd_stalled);
                        printf("dcd_stalled    = %d\n", m_core->v__DOT__thecpu__DOT__dcd_stalled);
Line 971... Line 978...
                        attroff(A_BOLD);
                        attroff(A_BOLD);
                mvprintw(ln, 0, "User Registers");
                mvprintw(ln, 0, "User Registers");
                mvprintw(ln, 42, "DCDR=%02x %s",
                mvprintw(ln, 42, "DCDR=%02x %s",
                        dcdR(), (m_core->v__DOT__thecpu__DOT__dcdR_wr)?"W":" ");
                        dcdR(), (m_core->v__DOT__thecpu__DOT__dcdR_wr)?"W":" ");
                mvprintw(ln, 62, "OPR =%02x %s%s",
                mvprintw(ln, 62, "OPR =%02x %s%s",
                        m_core->v__DOT__thecpu__DOT__opR,
                        m_core->v__DOT__thecpu__DOT__r_opR,
                        (m_core->v__DOT__thecpu__DOT__opR_wr)?"W":" ",
                        (m_core->v__DOT__thecpu__DOT__opR_wr)?"W":" ",
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"F":" ");
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"F":" ");
                ln++;
                ln++;
                dispreg(ln, 0, "uR0 ", m_state.m_uR[ 0], (m_cursor==28));
                dispreg(ln, 0, "uR0 ", m_state.m_uR[ 0], (m_cursor==28));
                dispreg(ln,20, "uR1 ", m_state.m_uR[ 1], (m_cursor==29));
                dispreg(ln,20, "uR1 ", m_state.m_uR[ 1], (m_cursor==29));
Line 1051... Line 1058...
                        ); ln++;
                        ); ln++;
 
 
                showins(ln, "Op",
                showins(ln, "Op",
                        op_ce(),
                        op_ce(),
                        m_core->v__DOT__thecpu__DOT__opvalid,
                        m_core->v__DOT__thecpu__DOT__opvalid,
                        m_core->v__DOT__thecpu__DOT__op_gie,
                        m_core->v__DOT__thecpu__DOT__r_op_gie,
                        m_core->v__DOT__thecpu__DOT__op_stall,
                        m_core->v__DOT__thecpu__DOT__op_stall,
                        op_pc(),
                        op_pc(),
#ifdef  OPT_VLIW
#ifdef  OPT_VLIW
                        m_core->v__DOT__thecpu__DOT__r_alu_phase
                        m_core->v__DOT__thecpu__DOT__r_alu_phase
#else
#else
Line 1065... Line 1072...
 
 
                if (m_core->v__DOT__thecpu__DOT__opvalid_mem) {
                if (m_core->v__DOT__thecpu__DOT__opvalid_mem) {
                        showins(ln, "Mm",
                        showins(ln, "Mm",
                                m_core->v__DOT__thecpu__DOT__mem_ce,
                                m_core->v__DOT__thecpu__DOT__mem_ce,
                                m_core->v__DOT__thecpu__DOT__mem_pc_valid,
                                m_core->v__DOT__thecpu__DOT__mem_pc_valid,
                                m_core->v__DOT__thecpu__DOT__alu_gie,
                                m_core->v__DOT__thecpu__DOT__r_alu_gie,
#ifdef  OPT_PIPELINED
#ifdef  OPT_PIPELINED
                                m_core->v__DOT__thecpu__DOT__mem_stall,
                                m_core->v__DOT__thecpu__DOT__mem_stall,
#else
#else
                                0,
                                0,
#endif
#endif
Line 1082... Line 1089...
                        );
                        );
                } else {
                } else {
                        showins(ln, "Al",
                        showins(ln, "Al",
                                m_core->v__DOT__thecpu__DOT__alu_ce,
                                m_core->v__DOT__thecpu__DOT__alu_ce,
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
                                m_core->v__DOT__thecpu__DOT__alu_gie,
                                m_core->v__DOT__thecpu__DOT__r_alu_gie,
#ifdef  OPT_PIPELINED
#ifdef  OPT_PIPELINED
                                m_core->v__DOT__thecpu__DOT__alu_stall,
                                m_core->v__DOT__thecpu__DOT__alu_stall,
#else
#else
                                0,
                                0,
#endif
#endif
Line 1107... Line 1114...
                                                m_core->o_qspi_sck,
                                                m_core->o_qspi_sck,
                                                m_core->o_qspi_dat);
                                                m_core->o_qspi_dat);
                */
                */
 
 
                int stb = m_core->o_wb_stb;
                int stb = m_core->o_wb_stb;
                if ((m_core->o_wb_addr & (-1<<20))!=1)
                m_core->i_wb_err = 0;
 
                if ((m_core->o_wb_addr & (-1<<20))!=(1<<20))
                        stb = 0;
                        stb = 0;
                if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb))
                if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb)) {
                        m_core->i_wb_ack = 1;
                        m_core->i_wb_ack = 1;
 
                        m_core->i_wb_err = 1;
 
                        bomb = true;
 
                        if (m_dbgfp) fprintf(m_dbgfp, "BOMB!! (Attempting to access %08x/%08x->%08x)\n", m_core->o_wb_addr,
 
                                (-1<<20), ((m_core->o_wb_addr)&(-1<<20)));
 
                }
 
 
                if ((dbg_flag)&&(m_dbgfp)) {
                if ((dbg_flag)&&(m_dbgfp)) {
                        fprintf(m_dbgfp, "DBG  %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s%s\n",
                        fprintf(m_dbgfp, "DBG  %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s%s\n",
                                (m_core->i_dbg_cyc)?"CYC":"   ",
                                (m_core->i_dbg_cyc)?"CYC":"   ",
                                (m_core->i_dbg_stb)?"STB":
                                (m_core->i_dbg_stb)?"STB":
Line 1124... Line 1137...
                                m_core->i_dbg_data,
                                m_core->i_dbg_data,
                                (m_core->o_dbg_ack)?"ACK":"   ",
                                (m_core->o_dbg_ack)?"ACK":"   ",
                                (m_core->o_dbg_stall)?"STALL":"     ",
                                (m_core->o_dbg_stall)?"STALL":"     ",
                                (m_core->o_dbg_data),
                                (m_core->o_dbg_data),
                                (m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
                                (m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
                                (m_core->v__DOT__cpu_dbg_stall)?"CPU-DBG_STALL":"",
                                (m_core->v__DOT__thecpu__DOT__r_halted)?"CPU-DBG_STALL":"",
                                (dcdvalid())?"DCDV ":"",
                                (dcdvalid())?"DCDV ":"",
                                (m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
                                (m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
                                (m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
                                (m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
                                (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GC":"  ",
                                (m_core->v__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_gbl)?"GC":"  ",
                                (m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LC":"  ",
                                (m_core->v__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_lcl)?"LC":"  ",
                                (m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
                                (m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
                                (m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"",
                                (m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"",
                                (m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"",
                                (m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"",
                                (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV ":"");
                                (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV ":"");
                        fprintf(m_dbgfp, " SYS %s %s %s @0x%08x/%d[0x%08x] %s [0x%08x]\n",
                        fprintf(m_dbgfp, " SYS %s %s %s @0x%08x/%d[0x%08x] %s [0x%08x]\n",
Line 1152... Line 1165...
                                dcd_ce(),
                                dcd_ce(),
                                m_core->v__DOT__thecpu__DOT__dcd_pc,
                                m_core->v__DOT__thecpu__DOT__dcd_pc,
                                op_ce(),
                                op_ce(),
                                op_pc(),
                                op_pc(),
                                dcdA()&0x01f,
                                dcdA()&0x01f,
                                m_core->v__DOT__thecpu__DOT__opR,
                                m_core->v__DOT__thecpu__DOT__r_opR,
                                m_core->v__DOT__cmd_halt,
                                m_core->v__DOT__cmd_halt,
                                m_core->v__DOT__cpu_halt,
                                m_core->v__DOT__cpu_halt,
                                m_core->v__DOT__thecpu__DOT__alu_ce,
                                m_core->v__DOT__thecpu__DOT__alu_ce,
                                m_core->v__DOT__thecpu__DOT__alu_valid,
                                m_core->v__DOT__thecpu__DOT__alu_valid,
                                m_core->v__DOT__thecpu__DOT__alu_wr,
                                m_core->v__DOT__thecpu__DOT__alu_wr,
Line 1190... Line 1203...
                                m_core->v__DOT__thecpu__DOT__w_iflags,
                                m_core->v__DOT__thecpu__DOT__w_iflags,
                                m_core->v__DOT__thecpu__DOT__w_uflags);
                                m_core->v__DOT__thecpu__DOT__w_uflags);
                        fprintf(m_dbgfp, "\tbrk=%s %d,%d\n",
                        fprintf(m_dbgfp, "\tbrk=%s %d,%d\n",
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
                                m_core->v__DOT__thecpu__DOT__break_en,
                                m_core->v__DOT__thecpu__DOT__break_en,
                                m_core->v__DOT__thecpu__DOT__op_break);
                                m_core->v__DOT__thecpu__DOT__r_op_break);
                } else if ((m_dbgfp)&&
                } else if ((m_dbgfp)&&
                                ((m_core->v__DOT__thecpu__DOT__op_break)
                                ((m_core->v__DOT__thecpu__DOT__r_op_break)
                                ||(m_core->v__DOT__thecpu__DOT__r_alu_illegal)
                                ||(m_core->v__DOT__thecpu__DOT__r_alu_illegal)
                                ||(m_core->v__DOT__thecpu__DOT__dcd_break))) {
                                ||(m_core->v__DOT__thecpu__DOT__dcd_break))) {
                        fprintf(m_dbgfp, "NOT SWITCHING TO GIE (gie = %d)\n", gie);
                        fprintf(m_dbgfp, "NOT SWITCHING TO GIE (gie = %d)\n", gie);
                        fprintf(m_dbgfp, "\tbrk=%s breaken=%d,dcdbreak=%d,opbreak=%d,alu_illegal=%d\n",
                        fprintf(m_dbgfp, "\tbrk=%s breaken=%d,dcdbreak=%d,opbreak=%d,alu_illegal=%d\n",
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
                                m_core->v__DOT__thecpu__DOT__break_en,
                                m_core->v__DOT__thecpu__DOT__break_en,
                                m_core->v__DOT__thecpu__DOT__dcd_break,
                                m_core->v__DOT__thecpu__DOT__dcd_break,
                                m_core->v__DOT__thecpu__DOT__op_break,
                                m_core->v__DOT__thecpu__DOT__r_op_break,
                                m_core->v__DOT__thecpu__DOT__r_alu_illegal);
                                m_core->v__DOT__thecpu__DOT__r_alu_illegal);
                }
                }
 
 
                if (m_dbgfp) {
                if (m_dbgfp) {
                        if(m_core->v__DOT__thecpu__DOT__clear_pipeline)
                        // if(m_core->v__DOT__thecpu__DOT__clear_pipeline)
                                fprintf(m_dbgfp, "\tClear Pipeline\n");
                                // fprintf(m_dbgfp, "\tClear Pipeline\n");
                        if(m_core->v__DOT__thecpu__DOT__new_pc)
                        if(m_core->v__DOT__thecpu__DOT__new_pc)
                                fprintf(m_dbgfp, "\tNew PC\n");
                                fprintf(m_dbgfp, "\tNew PC\n");
                }
                }
 
 
                if (m_dbgfp)
                if (m_dbgfp)
                        fprintf(m_dbgfp, "-----------  TICK ----------\n");
                        fprintf(m_dbgfp, "-----------  TICK (%08x) ----------%s\n",
 
                                m_core->v__DOT__jiffies__DOT__r_counter,
 
                                (bomb)?" BOMBED!!":"");
                if (false) {
                if (false) {
                        m_core->i_clk = 1;
                        m_core->i_clk = 1;
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
Line 1281... Line 1296...
#endif
#endif
                                );
                                );
                        dbgins("Op - ",
                        dbgins("Op - ",
                                op_ce(),
                                op_ce(),
                                m_core->v__DOT__thecpu__DOT__opvalid,
                                m_core->v__DOT__thecpu__DOT__opvalid,
                                m_core->v__DOT__thecpu__DOT__op_gie,
                                m_core->v__DOT__thecpu__DOT__r_op_gie,
                                m_core->v__DOT__thecpu__DOT__op_stall,
                                m_core->v__DOT__thecpu__DOT__op_stall,
                                op_pc(),
                                op_pc(),
#ifdef  OPT_VLIW
#ifdef  OPT_VLIW
                                m_core->v__DOT__thecpu__DOT__r_op_phase,
                                m_core->v__DOT__thecpu__DOT__r_op_phase,
#else
#else
Line 1298... Line 1313...
#endif
#endif
                                );
                                );
                        dbgins("Al - ",
                        dbgins("Al - ",
                                m_core->v__DOT__thecpu__DOT__alu_ce,
                                m_core->v__DOT__thecpu__DOT__alu_ce,
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
                                m_core->v__DOT__thecpu__DOT__alu_gie,
                                m_core->v__DOT__thecpu__DOT__r_alu_gie,
#ifdef  OPT_PIPELINED
#ifdef  OPT_PIPELINED
                                m_core->v__DOT__thecpu__DOT__alu_stall,
                                m_core->v__DOT__thecpu__DOT__alu_stall,
#else
#else
                                0,
                                0,
#endif
#endif
Line 1316... Line 1331...
                                m_core->v__DOT__thecpu__DOT__r_alu_illegal
                                m_core->v__DOT__thecpu__DOT__r_alu_illegal
#else
#else
                                false
                                false
#endif
#endif
                                );
                                );
 
                        if (m_core->v__DOT__thecpu__DOT__wr_reg_ce)
 
                                fprintf(m_dbgfp, "WB::Reg[%2x] <= %08x\n",
 
                                        m_core->v__DOT__thecpu__DOT__wr_reg_id,
 
                                        m_core->v__DOT__thecpu__DOT__wr_gpreg_vl);
 
 
                }
                }
 
 
                if ((m_dbgfp)&&((m_core->v__DOT__thecpu__DOT__div_valid)
                if ((m_dbgfp)&&((m_core->v__DOT__thecpu__DOT__div_valid)
                        ||(m_core->v__DOT__thecpu__DOT__div_ce)
                        ||(m_core->v__DOT__thecpu__DOT__div_ce)
Line 1332... Line 1351...
                                (m_core->v__DOT__thecpu__DOT__wr_reg_ce)?"REG-CE":"      ",
                                (m_core->v__DOT__thecpu__DOT__wr_reg_ce)?"REG-CE":"      ",
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
                                m_core->v__DOT__thecpu__DOT__wr_gpreg_vl,
                                m_core->v__DOT__thecpu__DOT__wr_gpreg_vl,
                                m_core->v__DOT__thecpu__DOT__wr_spreg_vl,
                                m_core->v__DOT__thecpu__DOT__wr_spreg_vl,
                                (m_core->v__DOT__thecpu__DOT__alu_pc_valid)?"PCV":"   ",
                                (m_core->v__DOT__thecpu__DOT__alu_pc_valid)?"PCV":"   ",
                                m_core->v__DOT__thecpu__DOT__alu_pc);
                                alu_pc());
 
 
                        fprintf(m_dbgfp, "ALU-PC: %08x %s %s\n",
                        fprintf(m_dbgfp, "ALU-PC: %08x %s %s\n",
                                m_core->v__DOT__thecpu__DOT__alu_pc,
                                alu_pc(),
                                (m_core->v__DOT__thecpu__DOT__r_alu_pc_valid)?"VALID":"",
                                (m_core->v__DOT__thecpu__DOT__r_alu_pc_valid)?"VALID":"",
                                (m_core->v__DOT__thecpu__DOT__alu_gie)?"ALU-GIE":"");
                                (m_core->v__DOT__thecpu__DOT__r_alu_gie)?"ALU-GIE":"");
                }
                }
 
 
                if ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
                if (m_core->v__DOT__dma_controller__DOT__dma_state) {
                        &&(!m_core->v__DOT__thecpu__DOT__clear_pipeline)) {
                        fprintf(m_dbgfp, "DMA[%d]%s%s%s%s@%08x,%08x [%d%d/%4d/%4d] -> [%d%d/%04d/%04d]\n",
 
                                m_core->v__DOT__dma_controller__DOT__dma_state,
 
                                (m_core->v__DOT__dc_cyc)?"C":" ",
 
                                (m_core->v__DOT__dc_stb)?"S":" ",
 
                                (m_core->v__DOT__dc_ack)?"A":" ",
 
                                (m_core->v__DOT__dc_err)?"E":" ",
 
                                m_core->v__DOT__dc_addr,
 
                                (m_core->v__DOT__dc_data),
 
                                m_core->v__DOT__dma_controller__DOT__last_read_request,
 
                                m_core->v__DOT__dma_controller__DOT__last_read_ack,
 
                                m_core->v__DOT__dma_controller__DOT__nracks,
 
                                m_core->v__DOT__dma_controller__DOT__nread,
 
                                m_core->v__DOT__dma_controller__DOT__last_write_request,
 
                                m_core->v__DOT__dma_controller__DOT__last_write_ack,
 
                                m_core->v__DOT__dma_controller__DOT__nwacks,
 
                                m_core->v__DOT__dma_controller__DOT__nwritten);
 
                }
 
                if (((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
 
                        ||(m_core->v__DOT__thecpu__DOT__mem_pc_valid))
 
                        &&(!m_core->v__DOT__thecpu__DOT__new_pc)) {
                        unsigned long iticks = m_tickcount - m_last_instruction_tickcount;
                        unsigned long iticks = m_tickcount - m_last_instruction_tickcount;
                        if (m_profile_fp) {
                        if (m_profile_fp) {
                                unsigned buf[2];
                                unsigned buf[2];
                                buf[0] = m_core->v__DOT__thecpu__DOT__alu_pc-1;
                                buf[0] = alu_pc();
                                buf[1] = iticks;
                                buf[1] = iticks;
                                fwrite(buf, sizeof(unsigned), 2, m_profile_fp);
                                fwrite(buf, sizeof(unsigned), 2, m_profile_fp);
                        }
                        }
                        m_last_instruction_tickcount = m_tickcount;
                        m_last_instruction_tickcount = m_tickcount;
                }
                }
Line 1370... Line 1408...
                return m_core->v__DOT__thecpu__DOT__op_pc-1;
                return m_core->v__DOT__thecpu__DOT__op_pc-1;
        }
        }
 
 
        bool    dcd_ce(void) {
        bool    dcd_ce(void) {
#ifdef  OPT_PIPELINED
#ifdef  OPT_PIPELINED
                return (m_core->v__DOT__thecpu__DOT__dcd_ce != 0);
                // return (m_core->v__DOT__thecpu__DOT__dcd_ce != 0);
 
                return ((!m_core->v__DOT__thecpu__DOT__r_dcdvalid)
 
                        ||(!m_core->v__DOT__thecpu__DOT__dcd_stalled))
 
                        &&(m_core->v__DOT__thecpu__DOT__new_pc);
#else
#else
                return (m_core->v__DOT__thecpu__DOT__pf_valid);
                return (m_core->v__DOT__thecpu__DOT__pf_valid);
#endif
#endif
        } bool  dcdvalid(void) {
        } bool  dcdvalid(void) {
                return (m_core->v__DOT__thecpu__DOT__r_dcdvalid !=0);
                return (m_core->v__DOT__thecpu__DOT__r_dcdvalid !=0);
Line 1417... Line 1458...
        bool    mem_stalled(void) {
        bool    mem_stalled(void) {
                bool    a, b, c, d, wr_write_cc, wr_write_pc, op_gie;
                bool    a, b, c, d, wr_write_cc, wr_write_pc, op_gie;
 
 
                wr_write_cc=((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x0f)==0x0e);
                wr_write_cc=((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x0f)==0x0e);
                wr_write_pc=((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x0f)==0x0f);
                wr_write_pc=((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x0f)==0x0f);
                op_gie = m_core->v__DOT__thecpu__DOT__op_gie;
                op_gie = m_core->v__DOT__thecpu__DOT__r_op_gie;
 
 
#ifdef  OPT_PIPELINED_BUS_ACCESS
#ifdef  OPT_PIPELINED_BUS_ACCESS
                //a = m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
                //a = m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
                a = mem_pipe_stalled();
                a = mem_pipe_stalled();
                b = (!m_core->v__DOT__thecpu__DOT__r_op_pipe)&&(mem_busy());
                b = (!m_core->v__DOT__thecpu__DOT__r_op_pipe)&&(mem_busy());
Line 1442... Line 1483...
                unsigned        r = op_pc();
                unsigned        r = op_pc();
                if (m_core->v__DOT__thecpu__DOT__opvalid)
                if (m_core->v__DOT__thecpu__DOT__opvalid)
                        r--;
                        r--;
                return r;
                return r;
                */
                */
                return m_core->v__DOT__thecpu__DOT__alu_pc-1;
                return m_core->v__DOT__thecpu__DOT__r_alu_pc-1;
        }
        }
 
 
#ifdef  OPT_PIPELINED_BUS_ACCESS
#ifdef  OPT_PIPELINED_BUS_ACCESS
        bool    mem_pipe_stalled(void) {
        bool    mem_pipe_stalled(void) {
                int     r = 0;
                int     r = 0;
                r = ((m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)
                r = ((m_core->v__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_gbl)
                 ||(m_core->v__DOT__thecpu__DOT__mem_cyc_lcl));
                 ||(m_core->v__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_lcl));
                r = r && ((m_core->v__DOT__thecpu__DOT__mem_stall)
                r = r && ((m_core->v__DOT__thecpu__DOT__mem_stall)
                        ||(
                        ||(
                                ((!m_core->v__DOT__thecpu__DOT__mem_stb_gbl)
                                ((!m_core->v__DOT__thecpu__DOT__mem_stb_gbl)
                                &&(!m_core->v__DOT__thecpu__DOT__mem_stb_lcl))));
                                &&(!m_core->v__DOT__thecpu__DOT__mem_stb_lcl))));
                return r;
                return r;
Line 1501... Line 1542...
                tick();
                tick();
                mvprintw(0,35, "%40s", "");
                mvprintw(0,35, "%40s", "");
                mvprintw(0,40, "wb_write -- complete");
                mvprintw(0,40, "wb_write -- complete");
 
 
 
 
                if (errcount >= 100)
                if (errcount >= 100) {
 
                        if (m_dbgfp) fprintf(m_dbgfp, "WB-WRITE: ERRCount = %d, BOMB!!\n", errcount);
                        bomb = true;
                        bomb = true;
        }
        }
 
        }
 
 
        unsigned long   wb_read(unsigned a) {
        unsigned long   wb_read(unsigned a) {
                unsigned int    v;
                unsigned int    v;
                int     errcount = 0;
                int     errcount = 0;
                mvprintw(0,35, "%40s", "");
                mvprintw(0,35, "%40s", "");
Line 1532... Line 1575...
                tick();
                tick();
 
 
                mvprintw(0,35, "%40s", "");
                mvprintw(0,35, "%40s", "");
                mvprintw(0,40, "wb_read = 0x%08x", v);
                mvprintw(0,40, "wb_read = 0x%08x", v);
 
 
                if (errcount >= 100)
                if (errcount >= 100) {
 
                        if (m_dbgfp) fprintf(m_dbgfp, "WB-WRITE: ERRCount = %d, BOMB!!\n", errcount);
                        bomb = true;
                        bomb = true;
 
                }
                return v;
                return v;
        }
        }
 
 
        void    cursor_up(void) {
        void    cursor_up(void) {
                if (m_cursor > 3)
                if (m_cursor > 3)
Line 1557... Line 1602...
 
 
        int     cursor(void) { return m_cursor; }
        int     cursor(void) { return m_cursor; }
 
 
        void    jump_to(ZIPI address) {
        void    jump_to(ZIPI address) {
                m_core->v__DOT__thecpu__DOT__pf_pc = address;
                m_core->v__DOT__thecpu__DOT__pf_pc = address;
                m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
                // m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
                m_core->v__DOT__thecpu__DOT__new_pc = 1;
                m_core->v__DOT__thecpu__DOT__new_pc = 1;
        }
        }
 
 
        void    dump_state(void) {
        void    dump_state(void) {
                if (m_dbgfp)
                if (m_dbgfp)
Line 1681... Line 1726...
                        case 15:
                        case 15:
                                tb->m_core->v__DOT__thecpu__DOT__ipc = v;
                                tb->m_core->v__DOT__thecpu__DOT__ipc = v;
                                if (!tb->m_core->v__DOT__thecpu__DOT__gie) {
                                if (!tb->m_core->v__DOT__thecpu__DOT__gie) {
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
                                        tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
                                        // tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
#ifdef  OPT_PIPELINED
#ifdef  OPT_PIPELINED
                                        tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
                                        // tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
                                        tb->m_core->v__DOT__thecpu__DOT__r_dcdvalid = 0;
                                        tb->m_core->v__DOT__thecpu__DOT__r_dcdvalid = 0;
#endif
#endif
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
                                }
                                }
                                break;
                                break;
                        case 31:
                        case 31:
                                tb->m_core->v__DOT__thecpu__DOT__upc = v;
                                tb->m_core->v__DOT__thecpu__DOT__upc = v;
                                if (tb->m_core->v__DOT__thecpu__DOT__gie) {
                                if (tb->m_core->v__DOT__thecpu__DOT__gie) {
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
                                        tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
                                        // tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
#ifdef  OPT_PIPELINED
#ifdef  OPT_PIPELINED
                                        tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
                                        // tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
                                        tb->m_core->v__DOT__thecpu__DOT__r_dcdvalid = 0;
                                        tb->m_core->v__DOT__thecpu__DOT__r_dcdvalid = 0;
#endif
#endif
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
                                }
                                }
                                break;
                                break;
Line 2172... Line 2217...
 
 
                tb->jump_to(entry);
                tb->jump_to(entry);
 
 
                // For debugging purposes: do we wish to skip some number of
                // For debugging purposes: do we wish to skip some number of
                // instructions to fast forward to a time of interest??
                // instructions to fast forward to a time of interest??
                for(int i=0; i<0x3f80; i++) {
                for(int i=0; i<0; i++) {
                        tb->m_core->v__DOT__cmd_halt = 0;
                        tb->m_core->v__DOT__cmd_halt = 0;
                        tb->tick();
                        tb->tick();
                }
                }
 
 
                int     chv = 'q';
                int     chv = 'q';

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.