///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: zippy_tb.cpp
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// Filename: zippy_tb.cpp
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//
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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//
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// Purpose: A bench simulator for the CPU. Eventually, you should be
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// Purpose: A bench simulator for the CPU. Eventually, you should be
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// able to give this program the name of a piece of compiled
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// able to give this program the name of a piece of compiled
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// code to load into memory. For now, we hand assemble with the
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// code to load into memory. For now, we hand assemble with the
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// computers help.
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// computers help.
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Tecnology, LLC
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// Gisselquist Tecnology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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#include <signal.h>
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#include <signal.h>
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#include <time.h>
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#include <time.h>
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#include <unistd.h>
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#include <unistd.h>
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|
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#include <ctype.h>
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#include <ctype.h>
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#include <ncurses.h>
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#include <ncurses.h>
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|
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#include "verilated.h"
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#include "verilated.h"
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#include "Vzipsystem.h"
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#include "Vzipsystem.h"
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|
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#include "testb.h"
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#include "testb.h"
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// #include "twoc.h"
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// #include "twoc.h"
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// #include "qspiflashsim.h"
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// #include "qspiflashsim.h"
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#include "memsim.h"
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#include "memsim.h"
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#include "zopcodes.h"
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#include "zopcodes.h"
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#include "zparser.h"
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#include "zparser.h"
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|
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#define CMD_REG 0
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#define CMD_REG 0
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#define CMD_DATA 1
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#define CMD_DATA 1
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#define CMD_HALT (1<<10)
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#define CMD_HALT (1<<10)
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#define CMD_STALL (1<<9)
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#define CMD_STALL (1<<9)
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#define CMD_STEP (1<<8)
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#define CMD_STEP (1<<8)
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#define CMD_INT (1<<7)
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#define CMD_INT (1<<7)
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#define CMD_RESET (1<<6)
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#define CMD_RESET (1<<6)
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|
|
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#define KEY_ESCAPE 27
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#define KEY_RETURN 10
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|
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// No particular "parameters" need definition or redefinition here.
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// No particular "parameters" need definition or redefinition here.
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class ZIPPY_TB : public TESTB<Vzipsystem> {
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class ZIPPY_TB : public TESTB<Vzipsystem> {
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public:
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public:
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unsigned long m_mem_size;
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unsigned long m_mem_size;
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MEMSIM m_mem;
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MEMSIM m_mem;
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// QSPIFLASHSIM m_flash;
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// QSPIFLASHSIM m_flash;
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FILE *dbg_fp;
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FILE *dbg_fp;
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bool dbg_flag, bomb;
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bool dbg_flag, bomb;
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int m_cursor;
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|
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ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
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ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
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//dbg_fp = fopen("dbg.txt", "w");
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// dbg_fp = fopen("dbg.txt", "w");
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dbg_fp = NULL;
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dbg_fp = NULL;
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dbg_flag = false;
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dbg_flag = false;
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bomb = false;
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bomb = false;
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m_cursor = 0;
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}
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}
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|
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void reset(void) {
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void reset(void) {
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// m_flash.debug(false);
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// m_flash.debug(false);
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TESTB<Vzipsystem>::reset();
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TESTB<Vzipsystem>::reset();
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}
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}
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|
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bool on_tick(void) {
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bool on_tick(void) {
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tick();
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tick();
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return true;
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return true;
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}
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}
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|
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void showval(int y, int x, const char *lbl, unsigned int v) {
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void showval(int y, int x, const char *lbl, unsigned int v, bool c) {
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if (c)
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mvprintw(y,x, ">%s> 0x%08x<", lbl, v);
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else
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mvprintw(y,x, "%s: 0x%08x", lbl, v);
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mvprintw(y,x, "%s: 0x%08x", lbl, v);
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}
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}
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|
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void dispreg(int y, int x, const char *n, unsigned int v) {
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void dispreg(int y, int x, const char *n, unsigned int v, bool c) {
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// 4,4,8,1 = 17 of 20, +3 = 19
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// 4,4,8,1 = 17 of 20, +3 = 19
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if (c)
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mvprintw(y, x, ">%s> 0x%08x<", n, v);
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else
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mvprintw(y, x, "%s: 0x%08x", n, v);
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mvprintw(y, x, "%s: 0x%08x", n, v);
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}
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}
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|
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void showreg(int y, int x, const char *n, int r) {
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void showreg(int y, int x, const char *n, int r, bool c) {
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// 4,4,8,1 = 17 of 20, +3 = 19
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// 4,4,8,1 = 17 of 20, +3 = 19
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if (c)
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mvprintw(y, x, ">%s> 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
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else
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mvprintw(y, x, "%s: 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
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mvprintw(y, x, "%s: 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
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addch( ((r == m_core->v__DOT__thecpu__DOT__dcdA)
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addch( ((r == m_core->v__DOT__thecpu__DOT__dcdA)
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&&(m_core->v__DOT__thecpu__DOT__dcdvalid)
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&&(m_core->v__DOT__thecpu__DOT__dcdvalid)
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&&(m_core->v__DOT__thecpu__DOT__dcdA_rd))
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&&(m_core->v__DOT__thecpu__DOT__dcdA_rd))
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?'a':' ');
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?'a':((c)?'<':' '));
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addch( ((r == m_core->v__DOT__thecpu__DOT__dcdB)
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addch( ((r == m_core->v__DOT__thecpu__DOT__dcdB)
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&&(m_core->v__DOT__thecpu__DOT__dcdvalid)
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&&(m_core->v__DOT__thecpu__DOT__dcdvalid)
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&&(m_core->v__DOT__thecpu__DOT__dcdB_rd))
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&&(m_core->v__DOT__thecpu__DOT__dcdB_rd))
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?'b':' ');
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?'b':((c)?'<':' '));
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addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
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addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
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&&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
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&&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
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?'W':' ');
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?'W':((c)?'<':' '));
|
}
|
}
|
|
|
void showins(int y, const char *lbl, const int ce, const int valid,
|
void showins(int y, const char *lbl, const int ce, const int valid,
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const int gie, const int stall, const unsigned int pc) {
|
const int gie, const int stall, const unsigned int pc) {
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char line[80];
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char line[80];
|
|
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if (ce)
|
if (ce)
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mvprintw(y, 0, "Ck ");
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mvprintw(y, 0, "Ck ");
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else
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else
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mvprintw(y, 0, " ");
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mvprintw(y, 0, " ");
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if (stall)
|
if (stall)
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printw("Stl ");
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printw("Stl ");
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else
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else
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printw(" ");
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printw(" ");
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printw("%s: 0x%08x", lbl, pc);
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printw("%s: 0x%08x", lbl, pc);
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|
|
if (valid) {
|
if (valid) {
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if (gie) attroff(A_BOLD);
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if (gie) attroff(A_BOLD);
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else attron(A_BOLD);
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else attron(A_BOLD);
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zipi_to_string(m_mem[pc], line);
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zipi_to_string(m_mem[pc], line);
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printw(" %-24s", &line[1]);
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printw(" %-24s", &line[1]);
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} else {
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} else {
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attroff(A_BOLD);
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attroff(A_BOLD);
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printw(" (0x%08x)%28s", m_mem[pc],"");
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printw(" (0x%08x)%28s", m_mem[pc],"");
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}
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}
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attroff(A_BOLD);
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attroff(A_BOLD);
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}
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}
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|
|
void dbgins(const char *lbl, const int ce, const int valid,
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void dbgins(const char *lbl, const int ce, const int valid,
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const int gie, const int stall, const unsigned int pc) {
|
const int gie, const int stall, const unsigned int pc) {
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char line[80];
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char line[80];
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|
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if (!dbg_fp)
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if (!dbg_fp)
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return;
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return;
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|
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if (ce)
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if (ce)
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fprintf(dbg_fp, "%s Ck ", lbl);
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fprintf(dbg_fp, "%s Ck ", lbl);
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else
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else
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fprintf(dbg_fp, "%s ", lbl);
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fprintf(dbg_fp, "%s ", lbl);
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if (stall)
|
if (stall)
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fprintf(dbg_fp, "Stl ");
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fprintf(dbg_fp, "Stl ");
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else
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else
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fprintf(dbg_fp, " ");
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fprintf(dbg_fp, " ");
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fprintf(dbg_fp, "0x%08x: ", pc);
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fprintf(dbg_fp, "0x%08x: ", pc);
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|
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if (valid) {
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if (valid) {
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zipi_to_string(m_mem[pc], line);
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zipi_to_string(m_mem[pc], line);
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fprintf(dbg_fp, " %-20s\n", &line[1]);
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fprintf(dbg_fp, " %-20s\n", &line[1]);
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} else {
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} else {
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fprintf(dbg_fp, " (0x%08x)\n", m_mem[pc]);
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fprintf(dbg_fp, " (0x%08x)\n", m_mem[pc]);
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}
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}
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}
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}
|
|
|
void show_state(void) {
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void show_state(void) {
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int ln= 0;
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int ln= 0;
|
|
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mvprintw(ln,0, "Peripherals-SS"); ln++;
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mvprintw(ln,0, "Peripherals-SS"); ln++;
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/*
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/*
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showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
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showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
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mvprintw(ln, 17, "%s%s",
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mvprintw(ln, 17, "%s%s",
|
((m_core->v__DOT__sys_cyc)
|
((m_core->v__DOT__sys_cyc)
|
&&(m_core->v__DOT__sys_we)
|
&&(m_core->v__DOT__sys_we)
|
&&(m_core->v__DOT__sys_addr == 0))?"W":" ",
|
&&(m_core->v__DOT__sys_addr == 0))?"W":" ",
|
(m_core->v__DOT__trap_int)?"I":" ");
|
(m_core->v__DOT__trap_int)?"I":" ");
|
*/
|
*/
|
showval(ln, 1, "PIC ", m_core->v__DOT__pic_data);
|
showval(ln, 0, "PIC ", m_core->v__DOT__pic_data, (m_cursor==0));
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showval(ln,21, "WDT ", m_core->v__DOT__watchdog__DOT__r_value);
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showval(ln,20, "WDT ", m_core->v__DOT__watchdog__DOT__r_value, (m_cursor==1));
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showval(ln,41, "CACH", m_core->v__DOT__manualcache__DOT__cache_base);
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showval(ln,40, "CACH", m_core->v__DOT__manualcache__DOT__cache_base, (m_cursor==2));
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showval(ln,61, "PIC2", m_core->v__DOT__ctri__DOT__r_int_state);
|
showval(ln,60, "PIC2", m_core->v__DOT__ctri__DOT__r_int_state, (m_cursor==3));
|
|
|
ln++;
|
ln++;
|
showval(ln, 1, "TMRA", m_core->v__DOT__timer_a__DOT__r_value);
|
showval(ln, 0, "TMRA", m_core->v__DOT__timer_a__DOT__r_value, (m_cursor==4));
|
showval(ln,21, "TMRB", m_core->v__DOT__timer_b__DOT__r_value);
|
showval(ln,20, "TMRB", m_core->v__DOT__timer_b__DOT__r_value, (m_cursor==5));
|
showval(ln,41, "TMRB", m_core->v__DOT__timer_c__DOT__r_value);
|
showval(ln,40, "TMRB", m_core->v__DOT__timer_c__DOT__r_value, (m_cursor==6));
|
showval(ln,61, "JIF ", m_core->v__DOT__jiffies__DOT__r_counter);
|
showval(ln,60, "JIF ", m_core->v__DOT__jiffies__DOT__r_counter, (m_cursor==7));
|
|
|
ln++;
|
ln++;
|
showval(ln, 1, "UTSK", m_core->v__DOT__utc_data);
|
showval(ln, 0, "UTSK", m_core->v__DOT__utc_data, (m_cursor==8));
|
showval(ln,21, "UOST", m_core->v__DOT__uoc_data);
|
showval(ln,20, "UOST", m_core->v__DOT__uoc_data, (m_cursor==9));
|
showval(ln,41, "UPST", m_core->v__DOT__upc_data);
|
showval(ln,40, "UPST", m_core->v__DOT__upc_data, (m_cursor==10));
|
showval(ln,61, "UICT", m_core->v__DOT__uic_data);
|
showval(ln,60, "UICT", m_core->v__DOT__uic_data, (m_cursor==11));
|
|
|
ln++;
|
ln++;
|
mvprintw(ln, 40, "%s %s",
|
mvprintw(ln, 40, "%s %s",
|
(m_core->v__DOT__cpu_halt)? "CPU-HALT": " ",
|
(m_core->v__DOT__cpu_halt)? "CPU-HALT": " ",
|
(m_core->v__DOT__cpu_reset)?"CPU-RESET":" "); ln++;
|
(m_core->v__DOT__cpu_reset)?"CPU-RESET":" "); ln++;
|
mvprintw(ln, 40, "%s %s %s 0x%02x",
|
mvprintw(ln, 40, "%s %s %s 0x%02x",
|
(m_core->v__DOT__cmd_halt)? "HALT": " ",
|
(m_core->v__DOT__cmd_halt)? "HALT": " ",
|
(m_core->v__DOT__cmd_reset)?"RESET":" ",
|
(m_core->v__DOT__cmd_reset)?"RESET":" ",
|
(m_core->v__DOT__cmd_step)? "STEP" :" ",
|
(m_core->v__DOT__cmd_step)? "STEP" :" ",
|
(m_core->v__DOT__cmd_addr)&0x3f);
|
(m_core->v__DOT__cmd_addr)&0x3f);
|
if (m_core->v__DOT__thecpu__DOT__gie)
|
if (m_core->v__DOT__thecpu__DOT__gie)
|
attroff(A_BOLD);
|
attroff(A_BOLD);
|
else
|
else
|
attron(A_BOLD);
|
attron(A_BOLD);
|
mvprintw(ln, 0, "Supervisor Registers");
|
mvprintw(ln, 0, "Supervisor Registers");
|
ln++;
|
ln++;
|
|
|
showreg(ln, 1, "sR0 ", 0);
|
showreg(ln, 0, "sR0 ", 0, (m_cursor==12));
|
showreg(ln,21, "sR1 ", 1);
|
showreg(ln,20, "sR1 ", 1, (m_cursor==13));
|
showreg(ln,41, "sR2 ", 2);
|
showreg(ln,40, "sR2 ", 2, (m_cursor==14));
|
showreg(ln,61, "sR3 ", 3); ln++;
|
showreg(ln,60, "sR3 ", 3, (m_cursor==15)); ln++;
|
|
|
showreg(ln, 1, "sR4 ", 4);
|
showreg(ln, 0, "sR4 ", 4, (m_cursor==16));
|
showreg(ln,21, "sR5 ", 5);
|
showreg(ln,20, "sR5 ", 5, (m_cursor==17));
|
showreg(ln,41, "sR6 ", 6);
|
showreg(ln,40, "sR6 ", 6, (m_cursor==18));
|
showreg(ln,61, "sR7 ", 7); ln++;
|
showreg(ln,60, "sR7 ", 7, (m_cursor==19)); ln++;
|
|
|
showreg(ln, 1, "sR8 ", 8);
|
showreg(ln, 0, "sR8 ", 8, (m_cursor==20));
|
showreg(ln,21, "sR9 ", 9);
|
showreg(ln,20, "sR9 ", 9, (m_cursor==21));
|
showreg(ln,41, "sR10", 10);
|
showreg(ln,40, "sR10", 10, (m_cursor==22));
|
showreg(ln,61, "sR11", 11); ln++;
|
showreg(ln,60, "sR11", 11, (m_cursor==23)); ln++;
|
|
|
showreg(ln, 1, "sR12", 12);
|
showreg(ln, 0, "sR12", 12, (m_cursor==24));
|
showreg(ln,21, "sSP ", 13);
|
showreg(ln,20, "sSP ", 13, (m_cursor==25));
|
mvprintw(ln,41, "sCC :%s%s%s%s%s%s%s%s",
|
mvprintw(ln,40, "sCC :%s%s%s%s%s%s%s%s",
|
(m_core->v__DOT__thecpu__DOT__trap)?"TRP":" ",
|
(m_core->v__DOT__thecpu__DOT__trap)?"TRP":" ",
|
(m_core->v__DOT__thecpu__DOT__step)?"STP":" ",
|
(m_core->v__DOT__thecpu__DOT__step)?"STP":" ",
|
(m_core->v__DOT__thecpu__DOT__sleep)?"SLP":" ",
|
(m_core->v__DOT__thecpu__DOT__sleep)?"SLP":" ",
|
(m_core->v__DOT__thecpu__DOT__gie)?"GIE":" ",
|
(m_core->v__DOT__thecpu__DOT__gie)?"GIE":" ",
|
(m_core->v__DOT__thecpu__DOT__iflags&8)?"V":" ",
|
(m_core->v__DOT__thecpu__DOT__iflags&8)?"V":" ",
|
(m_core->v__DOT__thecpu__DOT__iflags&4)?"N":" ",
|
(m_core->v__DOT__thecpu__DOT__iflags&4)?"N":" ",
|
(m_core->v__DOT__thecpu__DOT__iflags&2)?"C":" ",
|
(m_core->v__DOT__thecpu__DOT__iflags&2)?"C":" ",
|
(m_core->v__DOT__thecpu__DOT__iflags&1)?"Z":" ");
|
(m_core->v__DOT__thecpu__DOT__iflags&1)?"Z":" ");
|
mvprintw(ln,61, "sPC : 0x%08x", m_core->v__DOT__thecpu__DOT__ipc);
|
showval(ln,60, "sPC ", m_core->v__DOT__thecpu__DOT__ipc, (m_cursor==27));
|
ln++;
|
ln++;
|
|
|
if (m_core->v__DOT__thecpu__DOT__gie)
|
if (m_core->v__DOT__thecpu__DOT__gie)
|
attron(A_BOLD);
|
attron(A_BOLD);
|
else
|
else
|
attroff(A_BOLD);
|
attroff(A_BOLD);
|
mvprintw(ln, 0, "User Registers"); ln++;
|
mvprintw(ln, 0, "User Registers"); ln++;
|
showreg(ln, 1, "uR0 ", 16);
|
showreg(ln, 0, "uR0 ", 16, (m_cursor==28));
|
showreg(ln,21, "uR1 ", 17);
|
showreg(ln,20, "uR1 ", 17, (m_cursor==29));
|
showreg(ln,41, "uR2 ", 18);
|
showreg(ln,40, "uR2 ", 18, (m_cursor==30));
|
showreg(ln,61, "uR3 ", 19); ln++;
|
showreg(ln,60, "uR3 ", 19, (m_cursor==31)); ln++;
|
|
|
showreg(ln, 1, "uR4 ", 20);
|
showreg(ln, 0, "uR4 ", 20, (m_cursor==32));
|
showreg(ln,21, "uR5 ", 21);
|
showreg(ln,20, "uR5 ", 21, (m_cursor==33));
|
showreg(ln,41, "uR6 ", 22);
|
showreg(ln,40, "uR6 ", 22, (m_cursor==34));
|
showreg(ln,61, "uR7 ", 23); ln++;
|
showreg(ln,60, "uR7 ", 23, (m_cursor==35)); ln++;
|
|
|
showreg(ln, 1, "uR8 ", 24);
|
showreg(ln, 0, "uR8 ", 24, (m_cursor==36));
|
showreg(ln,21, "uR9 ", 25);
|
showreg(ln,20, "uR9 ", 25, (m_cursor==37));
|
showreg(ln,41, "uR10", 26);
|
showreg(ln,40, "uR10", 26, (m_cursor==38));
|
showreg(ln,61, "uR11", 27); ln++;
|
showreg(ln,60, "uR11", 27, (m_cursor==39)); ln++;
|
|
|
showreg(ln, 1, "uR12", 28);
|
showreg(ln, 0, "uR12", 28, (m_cursor==40));
|
showreg(ln,21, "uSP ", 29);
|
showreg(ln,20, "uSP ", 29, (m_cursor==41));
|
mvprintw(ln,41, "uCC :%s%s%s%s%s%s%s%s",
|
mvprintw(ln,40, "uCC :%s%s%s%s%s%s%s%s",
|
(m_core->v__DOT__thecpu__DOT__trap)?"TRP":" ",
|
(m_core->v__DOT__thecpu__DOT__trap)?"TRP":" ",
|
(m_core->v__DOT__thecpu__DOT__step)?"STP":" ",
|
(m_core->v__DOT__thecpu__DOT__step)?"STP":" ",
|
(m_core->v__DOT__thecpu__DOT__sleep)?"SLP":" ",
|
(m_core->v__DOT__thecpu__DOT__sleep)?"SLP":" ",
|
(m_core->v__DOT__thecpu__DOT__gie)?"GIE":" ",
|
(m_core->v__DOT__thecpu__DOT__gie)?"GIE":" ",
|
(m_core->v__DOT__thecpu__DOT__flags&8)?"V":" ",
|
(m_core->v__DOT__thecpu__DOT__flags&8)?"V":" ",
|
(m_core->v__DOT__thecpu__DOT__flags&4)?"N":" ",
|
(m_core->v__DOT__thecpu__DOT__flags&4)?"N":" ",
|
(m_core->v__DOT__thecpu__DOT__flags&2)?"C":" ",
|
(m_core->v__DOT__thecpu__DOT__flags&2)?"C":" ",
|
(m_core->v__DOT__thecpu__DOT__flags&1)?"Z":" ");
|
(m_core->v__DOT__thecpu__DOT__flags&1)?"Z":" ");
|
mvprintw(ln,61, "uPC : 0x%08x", m_core->v__DOT__thecpu__DOT__upc);
|
showval(ln,60, "uPC ", m_core->v__DOT__thecpu__DOT__upc, (m_cursor==43));
|
|
|
attroff(A_BOLD);
|
attroff(A_BOLD);
|
ln+=1;
|
ln+=1;
|
|
|
mvprintw(ln, 0, "PFPIPE: rda=%08x/%d, bas=%08x, off=%08x, nv=%03x, ackw=%d",
|
mvprintw(ln, 0, "PFPIPE: rda=%08x/%d, bas=%08x, off=%08x, nv=%03x, ackw=%d",
|
m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr,
|
m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr,
|
m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
|
m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
|
m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_base,
|
m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_base,
|
m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_offset,
|
m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_offset,
|
m_core->v__DOT__thecpu__DOT__pf__DOT__r_nvalid,
|
m_core->v__DOT__thecpu__DOT__pf__DOT__r_nvalid,
|
m_core->v__DOT__thecpu__DOT__pf__DOT__r_acks_waiting);
|
m_core->v__DOT__thecpu__DOT__pf__DOT__r_acks_waiting);
|
ln++;
|
ln++;
|
mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
|
mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
|
(m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":" ",
|
(m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":" ",
|
(m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":" ",
|
(m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":" ",
|
" ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":" ",
|
" ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":" ",
|
(m_core->v__DOT__thecpu__DOT__pf_addr),
|
(m_core->v__DOT__thecpu__DOT__pf_addr),
|
0, // (m_core->v__DOT__thecpu__DOT__pf_data),
|
0, // (m_core->v__DOT__thecpu__DOT__pf_data),
|
(m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":" ",
|
(m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":" ",
|
(m_core->v__DOT__cpu_stall)?"STL":" ",
|
(m_core->v__DOT__cpu_stall)?"STL":" ",
|
(m_core->v__DOT__wb_data)); ln++;
|
(m_core->v__DOT__wb_data)); ln++;
|
|
|
mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
|
mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
|
(m_core->v__DOT__thecpu__DOT__mem_cyc)?"CYC":" ",
|
(m_core->v__DOT__thecpu__DOT__mem_cyc)?"CYC":" ",
|
(m_core->v__DOT__thecpu__DOT__mem_stb)?"STB":" ",
|
(m_core->v__DOT__thecpu__DOT__mem_stb)?"STB":" ",
|
(m_core->v__DOT__thecpu__DOT__mem_we )?"WE":" ",
|
(m_core->v__DOT__thecpu__DOT__mem_we )?"WE":" ",
|
(m_core->v__DOT__thecpu__DOT__mem_addr),
|
(m_core->v__DOT__thecpu__DOT__mem_addr),
|
(m_core->v__DOT__thecpu__DOT__mem_data),
|
(m_core->v__DOT__thecpu__DOT__mem_data),
|
(m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":" ",
|
(m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":" ",
|
(m_core->v__DOT__cpu_stall)?"STL":" ",
|
(m_core->v__DOT__cpu_stall)?"STL":" ",
|
(m_core->v__DOT__thecpu__DOT__mem_result)); ln++;
|
(m_core->v__DOT__thecpu__DOT__mem_result)); ln++;
|
|
|
mvprintw(ln, 0, "SYSBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
|
mvprintw(ln, 0, "SYSBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
|
(m_core->o_wb_cyc)?"CYC":" ",
|
(m_core->o_wb_cyc)?"CYC":" ",
|
(m_core->o_wb_stb)?"STB":" ",
|
(m_core->o_wb_stb)?"STB":" ",
|
(m_core->o_wb_we )?"WE":" ",
|
(m_core->o_wb_we )?"WE":" ",
|
(m_core->o_wb_addr),
|
(m_core->o_wb_addr),
|
(m_core->o_wb_data),
|
(m_core->o_wb_data),
|
(m_core->i_wb_ack)?"ACK":" ",
|
(m_core->i_wb_ack)?"ACK":" ",
|
(m_core->i_wb_stall)?"STL":" ",
|
(m_core->i_wb_stall)?"STL":" ",
|
(m_core->i_wb_data)); ln+=2;
|
(m_core->i_wb_data)); ln+=2;
|
|
|
showins(ln, "I ",
|
showins(ln, "I ",
|
!m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
!m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
m_core->v__DOT__thecpu__DOT__pf_valid,
|
m_core->v__DOT__thecpu__DOT__pf_valid,
|
//m_core->v__DOT__thecpu__DOT__instruction_gie,
|
//m_core->v__DOT__thecpu__DOT__instruction_gie,
|
m_core->v__DOT__thecpu__DOT__gie,
|
m_core->v__DOT__thecpu__DOT__gie,
|
0,
|
0,
|
// m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
|
// m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
|
m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
|
m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
|
|
|
showins(ln, "Dc",
|
showins(ln, "Dc",
|
m_core->v__DOT__thecpu__DOT__dcd_ce,
|
m_core->v__DOT__thecpu__DOT__dcd_ce,
|
m_core->v__DOT__thecpu__DOT__dcdvalid,
|
m_core->v__DOT__thecpu__DOT__dcdvalid,
|
m_core->v__DOT__thecpu__DOT__dcd_gie,
|
m_core->v__DOT__thecpu__DOT__dcd_gie,
|
m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
|
m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
|
|
|
showins(ln, "Op",
|
showins(ln, "Op",
|
m_core->v__DOT__thecpu__DOT__op_ce,
|
m_core->v__DOT__thecpu__DOT__op_ce,
|
m_core->v__DOT__thecpu__DOT__opvalid,
|
m_core->v__DOT__thecpu__DOT__opvalid,
|
m_core->v__DOT__thecpu__DOT__op_gie,
|
m_core->v__DOT__thecpu__DOT__op_gie,
|
m_core->v__DOT__thecpu__DOT__op_stall,
|
m_core->v__DOT__thecpu__DOT__op_stall,
|
m_core->v__DOT__thecpu__DOT__op_pc-1); ln++;
|
m_core->v__DOT__thecpu__DOT__op_pc-1); ln++;
|
|
|
showins(ln, "Al",
|
showins(ln, "Al",
|
m_core->v__DOT__thecpu__DOT__alu_ce,
|
m_core->v__DOT__thecpu__DOT__alu_ce,
|
m_core->v__DOT__thecpu__DOT__alu_pc_valid,
|
m_core->v__DOT__thecpu__DOT__alu_pc_valid,
|
m_core->v__DOT__thecpu__DOT__alu_gie,
|
m_core->v__DOT__thecpu__DOT__alu_gie,
|
m_core->v__DOT__thecpu__DOT__alu_stall,
|
m_core->v__DOT__thecpu__DOT__alu_stall,
|
m_core->v__DOT__thecpu__DOT__alu_pc-1); ln++;
|
m_core->v__DOT__thecpu__DOT__alu_pc-1); ln++;
|
|
|
mvprintw(ln-5, 48,"%s %s",
|
mvprintw(ln-5, 48,"%s %s",
|
(m_core->v__DOT__thecpu__DOT__op_break)?"OB":" ",
|
(m_core->v__DOT__thecpu__DOT__op_break)?"OB":" ",
|
(m_core->v__DOT__thecpu__DOT__clear_pipeline)?"CLRP":" ");
|
(m_core->v__DOT__thecpu__DOT__clear_pipeline)?"CLRP":" ");
|
mvprintw(ln-4, 48,
|
mvprintw(ln-4, 48,
|
(m_core->v__DOT__thecpu__DOT__new_pc)?"new-pc":" ");
|
(m_core->v__DOT__thecpu__DOT__new_pc)?"new-pc":" ");
|
printw("(%s:%02x,%x)",
|
printw("(%s:%02x,%x)",
|
(m_core->v__DOT__thecpu__DOT__set_cond)?"SET":" ",
|
(m_core->v__DOT__thecpu__DOT__set_cond)?"SET":" ",
|
(m_core->v__DOT__thecpu__DOT__opF&0x0ff),
|
(m_core->v__DOT__thecpu__DOT__opF&0x0ff),
|
(m_core->v__DOT__thecpu__DOT__op_gie)
|
(m_core->v__DOT__thecpu__DOT__op_gie)
|
? (m_core->v__DOT__thecpu__DOT__w_uflags)
|
? (m_core->v__DOT__thecpu__DOT__w_uflags)
|
: (m_core->v__DOT__thecpu__DOT__w_iflags));
|
: (m_core->v__DOT__thecpu__DOT__w_iflags));
|
|
|
printw("(%s%s%s:%02x)",
|
printw("(%s%s%s:%02x)",
|
(m_core->v__DOT__thecpu__DOT__opF_wr)?"OF":" ",
|
(m_core->v__DOT__thecpu__DOT__opF_wr)?"OF":" ",
|
(m_core->v__DOT__thecpu__DOT__alF_wr)?"FL":" ",
|
(m_core->v__DOT__thecpu__DOT__alF_wr)?"FL":" ",
|
(m_core->v__DOT__thecpu__DOT__wr_flags_ce)?"W":" ",
|
(m_core->v__DOT__thecpu__DOT__wr_flags_ce)?"W":" ",
|
(m_core->v__DOT__thecpu__DOT__alu_flags));
|
(m_core->v__DOT__thecpu__DOT__alu_flags));
|
/*
|
/*
|
mvprintw(ln-3, 48, "dcdI : 0x%08x",
|
mvprintw(ln-3, 48, "dcdI : 0x%08x",
|
m_core->v__DOT__thecpu__DOT__dcdI);
|
m_core->v__DOT__thecpu__DOT__dcdI);
|
mvprintw(ln-2, 48, "r_opB: 0x%08x",
|
mvprintw(ln-2, 48, "r_opB: 0x%08x",
|
m_core->v__DOT__thecpu__DOT__opB);
|
m_core->v__DOT__thecpu__DOT__opB);
|
*/
|
*/
|
mvprintw(ln-3, 48, "Op(%x)%8x,%8x->",
|
mvprintw(ln-3, 48, "Op(%x)%8x,%8x->",
|
m_core->v__DOT__thecpu__DOT__opn,
|
m_core->v__DOT__thecpu__DOT__opn,
|
m_core->v__DOT__thecpu__DOT__r_opA,
|
m_core->v__DOT__thecpu__DOT__r_opA,
|
m_core->v__DOT__thecpu__DOT__r_opB);
|
m_core->v__DOT__thecpu__DOT__r_opB);
|
if (m_core->v__DOT__thecpu__DOT__alu_valid)
|
if (m_core->v__DOT__thecpu__DOT__alu_valid)
|
printw("%08x", m_core->v__DOT__thecpu__DOT__alu_result);
|
printw("%08x", m_core->v__DOT__thecpu__DOT__alu_result);
|
else
|
else
|
printw("%8s","");
|
printw("%8s","");
|
mvprintw(ln-1, 48, "MEM: %s%s %s%s %s %-5s",
|
mvprintw(ln-1, 48, "MEM: %s%s %s%s %s %-5s",
|
(m_core->v__DOT__thecpu__DOT__opvalid_mem)?"M":" ",
|
(m_core->v__DOT__thecpu__DOT__opvalid_mem)?"M":" ",
|
(m_core->v__DOT__thecpu__DOT__mem_ce)?"CE":" ",
|
(m_core->v__DOT__thecpu__DOT__mem_ce)?"CE":" ",
|
(m_core->v__DOT__thecpu__DOT__mem_we)?"Wr ":"Rd ",
|
(m_core->v__DOT__thecpu__DOT__mem_we)?"Wr ":"Rd ",
|
(m_core->v__DOT__thecpu__DOT__mem_stalled)?"PIPE":" ",
|
(m_core->v__DOT__thecpu__DOT__mem_stalled)?"PIPE":" ",
|
(m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV":" ",
|
(m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV":" ",
|
zop_regstr[(m_core->v__DOT__thecpu__DOT__mem_wreg&0x1f)^0x10]);
|
zop_regstr[(m_core->v__DOT__thecpu__DOT__mem_wreg&0x1f)^0x10]);
|
}
|
}
|
|
|
unsigned int cmd_read(unsigned int a) {
|
unsigned int cmd_read(unsigned int a) {
|
if (dbg_fp) {
|
if (dbg_fp) {
|
dbg_flag= true;
|
dbg_flag= true;
|
fprintf(dbg_fp, "CMD-READ(%d)\n", a);
|
fprintf(dbg_fp, "CMD-READ(%d)\n", a);
|
}
|
}
|
wb_write(CMD_REG, CMD_HALT|(a&0x3f));
|
wb_write(CMD_REG, CMD_HALT|(a&0x3f));
|
while((wb_read(CMD_REG) & CMD_STALL) == 0)
|
while((wb_read(CMD_REG) & CMD_STALL) == 0)
|
;
|
;
|
unsigned int v = wb_read(CMD_DATA);
|
unsigned int v = wb_read(CMD_DATA);
|
|
|
if (dbg_flag)
|
if (dbg_flag)
|
fprintf(dbg_fp, "CMD-READ(%d) = 0x%08x\n", a,
|
fprintf(dbg_fp, "CMD-READ(%d) = 0x%08x\n", a,
|
v);
|
v);
|
dbg_flag = false;
|
dbg_flag = false;
|
return v;
|
return v;
|
}
|
}
|
|
|
|
void cmd_write(unsigned int a, int v) {
|
|
if ((a&0x0f)==0x0f)
|
|
dbg_flag = true;
|
|
wb_write(CMD_REG, CMD_HALT|(a&0x3f));
|
|
while((wb_read(CMD_REG) & CMD_STALL) == 0)
|
|
;
|
|
if (dbg_flag)
|
|
fprintf(dbg_fp, "CMD-WRITE(%d) <= 0x%08x\n", a, v);
|
|
wb_write(CMD_DATA, v);
|
|
}
|
|
|
bool halted(void) {
|
bool halted(void) {
|
return (m_core->v__DOT__cmd_halt != 0);
|
return (m_core->v__DOT__cmd_halt != 0);
|
}
|
}
|
|
|
void read_state(void) {
|
void read_state(void) {
|
int ln= 0;
|
int ln= 0;
|
|
bool gie;
|
|
|
mvprintw(ln,0, "Peripherals-RS"); ln++;
|
if (m_cursor < 0)
|
showval(ln, 1, "PIC ", cmd_read(32+ 0));
|
m_cursor = 0;
|
showval(ln,21, "WDT ", cmd_read(32+ 1));
|
else if (m_cursor >= 44)
|
showval(ln,41, "CACH", cmd_read(32+ 2));
|
m_cursor = 43;
|
showval(ln,61, "PIC2", cmd_read(32+ 3));
|
|
ln++;
|
mvprintw(ln,0, "Peripherals-RS");
|
showval(ln, 1, "TMRA", cmd_read(32+ 4));
|
mvprintw(ln,40,"%-40s", "CPU State: ");
|
showval(ln,21, "TMRB", cmd_read(32+ 5));
|
{
|
showval(ln,41, "TMRC", cmd_read(32+ 6));
|
unsigned int v = wb_read(CMD_REG);
|
showval(ln,61, "JIF ", cmd_read(32+ 7));
|
mvprintw(ln,51, "");
|
|
if (v & 0x010000)
|
ln++;
|
printw("EXT-INT ");
|
showval(ln, 1, "UTSK", cmd_read(32+12));
|
if ((v & 0x003000) == 0x03000)
|
showval(ln,21, "UMST", cmd_read(32+13));
|
printw("Halted ");
|
showval(ln,41, "UPST", cmd_read(32+14));
|
else if (v & 0x001000)
|
showval(ln,61, "UAST", cmd_read(32+15));
|
printw("Sleeping ");
|
|
else if (v & 0x002000)
|
|
printw("Supervisor Mod ");
|
|
if (v & 0x008000)
|
|
printw("Break-Enabled ");
|
|
if (v & 0x000080)
|
|
printw("PIC Enabled ");
|
|
} ln++;
|
|
showval(ln, 0, "PIC ", cmd_read(32+ 0), (m_cursor==0));
|
|
showval(ln,20, "WDT ", cmd_read(32+ 1), (m_cursor==1));
|
|
showval(ln,40, "CACH", cmd_read(32+ 2), (m_cursor==2));
|
|
showval(ln,60, "PIC2", cmd_read(32+ 3), (m_cursor==3));
|
|
ln++;
|
|
showval(ln, 0, "TMRA", cmd_read(32+ 4), (m_cursor==4));
|
|
showval(ln,20, "TMRB", cmd_read(32+ 5), (m_cursor==5));
|
|
showval(ln,40, "TMRC", cmd_read(32+ 6), (m_cursor==6));
|
|
showval(ln,60, "JIF ", cmd_read(32+ 7), (m_cursor==7));
|
|
|
|
ln++;
|
|
showval(ln, 0, "UTSK", cmd_read(32+12), (m_cursor==8));
|
|
showval(ln,20, "UMST", cmd_read(32+13), (m_cursor==9));
|
|
showval(ln,40, "UPST", cmd_read(32+14), (m_cursor==10));
|
|
showval(ln,60, "UICT", cmd_read(32+15), (m_cursor==11));
|
|
|
ln++;
|
ln++;
|
ln++;
|
ln++;
|
unsigned int cc = cmd_read(14);
|
unsigned int cc = cmd_read(14);
|
if (dbg_fp) fprintf(dbg_fp, "CC = %08x, gie = %d\n", cc,
|
if (dbg_fp) fprintf(dbg_fp, "CC = %08x, gie = %d\n", cc,
|
m_core->v__DOT__thecpu__DOT__gie);
|
m_core->v__DOT__thecpu__DOT__gie);
|
if (cc & 0x020)
|
gie = (cc & 0x020);
|
|
if (gie)
|
attroff(A_BOLD);
|
attroff(A_BOLD);
|
else
|
else
|
attron(A_BOLD);
|
attron(A_BOLD);
|
mvprintw(ln, 0, "Supervisor Registers");
|
mvprintw(ln, 0, "Supervisor Registers");
|
ln++;
|
ln++;
|
|
|
dispreg(ln, 1, "sR0 ", cmd_read(0));
|
dispreg(ln, 0, "sR0 ", cmd_read(0), (m_cursor==12));
|
dispreg(ln,21, "sR1 ", cmd_read(1));
|
dispreg(ln,20, "sR1 ", cmd_read(1), (m_cursor==13));
|
dispreg(ln,41, "sR2 ", cmd_read(2));
|
dispreg(ln,40, "sR2 ", cmd_read(2), (m_cursor==14));
|
dispreg(ln,61, "sR3 ", cmd_read(3)); ln++;
|
dispreg(ln,60, "sR3 ", cmd_read(3), (m_cursor==15)); ln++;
|
|
|
dispreg(ln, 1, "sR4 ", cmd_read(4));
|
dispreg(ln, 0, "sR4 ", cmd_read(4), (m_cursor==16));
|
dispreg(ln,21, "sR5 ", cmd_read(5));
|
dispreg(ln,20, "sR5 ", cmd_read(5), (m_cursor==17));
|
dispreg(ln,41, "sR6 ", cmd_read(6));
|
dispreg(ln,40, "sR6 ", cmd_read(6), (m_cursor==18));
|
dispreg(ln,61, "sR7 ", cmd_read(7)); ln++;
|
dispreg(ln,60, "sR7 ", cmd_read(7), (m_cursor==19)); ln++;
|
|
|
dispreg(ln, 1, "sR8 ", cmd_read( 8));
|
dispreg(ln, 0, "sR8 ", cmd_read( 8), (m_cursor==20));
|
dispreg(ln,21, "sR9 ", cmd_read( 9));
|
dispreg(ln,20, "sR9 ", cmd_read( 9), (m_cursor==21));
|
dispreg(ln,41, "sR10", cmd_read(10));
|
dispreg(ln,40, "sR10", cmd_read(10), (m_cursor==22));
|
dispreg(ln,61, "sR11", cmd_read(11)); ln++;
|
dispreg(ln,60, "sR11", cmd_read(11), (m_cursor==23)); ln++;
|
|
|
dispreg(ln, 1, "sR12", cmd_read(12));
|
dispreg(ln, 0, "sR12", cmd_read(12), (m_cursor==24));
|
dispreg(ln,21, "sSP ", cmd_read(13));
|
dispreg(ln,20, "sSP ", cmd_read(13), (m_cursor==25));
|
|
|
mvprintw(ln,41, "sCC :%s%s%s%s%s%s%s",
|
mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s%s",
|
(cc & 0x040)?"STP":" ",
|
(m_cursor==26)?">":" ",
|
(cc & 0x020)?"GIE":" ",
|
(cc & 0x100)?"TP":" ",
|
(cc & 0x010)?"SLP":" ",
|
(cc & 0x040)?"ST":" ",
|
|
(cc & 0x020)?"IE":" ",
|
|
(cc & 0x010)?"SL":" ",
|
(cc&8)?"V":" ",
|
(cc&8)?"V":" ",
|
(cc&4)?"N":" ",
|
(cc&4)?"N":" ",
|
(cc&2)?"C":" ",
|
(cc&2)?"C":" ",
|
(cc&1)?"Z":" ");
|
(cc&1)?"Z":" ");
|
mvprintw(ln,61, "sPC : 0x%08x", cmd_read(15));
|
dispreg(ln,60, "sPC ", cmd_read(15), (m_cursor==27));
|
ln++;
|
ln++;
|
|
|
if (cc & 0x020)
|
if (gie)
|
attron(A_BOLD);
|
attron(A_BOLD);
|
else
|
else
|
attroff(A_BOLD);
|
attroff(A_BOLD);
|
mvprintw(ln, 0, "User Registers"); ln++;
|
mvprintw(ln, 0, "User Registers"); ln++;
|
dispreg(ln, 1, "uR0 ", cmd_read(16));
|
dispreg(ln, 0, "uR0 ", cmd_read(16), (m_cursor==28));
|
dispreg(ln,21, "uR1 ", cmd_read(17));
|
dispreg(ln,20, "uR1 ", cmd_read(17), (m_cursor==29));
|
dispreg(ln,41, "uR2 ", cmd_read(18));
|
dispreg(ln,40, "uR2 ", cmd_read(18), (m_cursor==30));
|
dispreg(ln,61, "uR3 ", cmd_read(19)); ln++;
|
dispreg(ln,60, "uR3 ", cmd_read(19), (m_cursor==31)); ln++;
|
|
|
dispreg(ln, 1, "uR4 ", cmd_read(20));
|
dispreg(ln, 0, "uR4 ", cmd_read(20), (m_cursor==32));
|
dispreg(ln,21, "uR5 ", cmd_read(21));
|
dispreg(ln,20, "uR5 ", cmd_read(21), (m_cursor==33));
|
dispreg(ln,41, "uR6 ", cmd_read(22));
|
dispreg(ln,40, "uR6 ", cmd_read(22), (m_cursor==34));
|
dispreg(ln,61, "uR7 ", cmd_read(23)); ln++;
|
dispreg(ln,60, "uR7 ", cmd_read(23), (m_cursor==35)); ln++;
|
|
|
dispreg(ln, 1, "uR8 ", cmd_read(24));
|
dispreg(ln, 0, "uR8 ", cmd_read(24), (m_cursor==36));
|
dispreg(ln,21, "uR9 ", cmd_read(25));
|
dispreg(ln,20, "uR9 ", cmd_read(25), (m_cursor==37));
|
dispreg(ln,41, "uR10", cmd_read(26));
|
dispreg(ln,40, "uR10", cmd_read(26), (m_cursor==38));
|
dispreg(ln,61, "uR11", cmd_read(27)); ln++;
|
dispreg(ln,60, "uR11", cmd_read(27), (m_cursor==39)); ln++;
|
|
|
dispreg(ln, 1, "uR12", cmd_read(28));
|
dispreg(ln, 0, "uR12", cmd_read(28), (m_cursor==40));
|
dispreg(ln,21, "uSP ", cmd_read(29));
|
dispreg(ln,20, "uSP ", cmd_read(29), (m_cursor==41));
|
cc = cmd_read(30);
|
cc = cmd_read(30);
|
mvprintw(ln,41, "uCC :%s%s%s%s%s%s%s",
|
mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s%s",
|
(cc&0x040)?"STP":" ",
|
(m_cursor == 42)?">":" ",
|
(cc&0x020)?"GIE":" ",
|
(cc&0x100)?"TP":" ",
|
(cc&0x010)?"SLP":" ",
|
(cc&0x040)?"ST":" ",
|
|
(cc&0x020)?"IE":" ",
|
|
(cc&0x010)?"SL":" ",
|
(cc&8)?"V":" ",
|
(cc&8)?"V":" ",
|
(cc&4)?"N":" ",
|
(cc&4)?"N":" ",
|
(cc&2)?"C":" ",
|
(cc&2)?"C":" ",
|
(cc&1)?"Z":" ");
|
(cc&1)?"Z":" ");
|
mvprintw(ln,61, "uPC : 0x%08x", cmd_read(31));
|
dispreg(ln,60, "uPC ", cmd_read(31), (m_cursor==43));
|
|
|
attroff(A_BOLD);
|
attroff(A_BOLD);
|
ln+=2;
|
ln+=2;
|
|
|
ln+=3;
|
ln+=3;
|
|
|
showins(ln, "I ",
|
showins(ln, "I ",
|
!m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
!m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
m_core->v__DOT__thecpu__DOT__pf_valid,
|
m_core->v__DOT__thecpu__DOT__pf_valid,
|
m_core->v__DOT__thecpu__DOT__gie,
|
m_core->v__DOT__thecpu__DOT__gie,
|
0,
|
0,
|
// m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
|
// m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
|
m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
|
m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
|
|
|
showins(ln, "Dc",
|
showins(ln, "Dc",
|
m_core->v__DOT__thecpu__DOT__dcd_ce,
|
m_core->v__DOT__thecpu__DOT__dcd_ce,
|
m_core->v__DOT__thecpu__DOT__dcdvalid,
|
m_core->v__DOT__thecpu__DOT__dcdvalid,
|
m_core->v__DOT__thecpu__DOT__dcd_gie,
|
m_core->v__DOT__thecpu__DOT__dcd_gie,
|
m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
|
m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
|
|
|
showins(ln, "Op",
|
showins(ln, "Op",
|
m_core->v__DOT__thecpu__DOT__op_ce,
|
m_core->v__DOT__thecpu__DOT__op_ce,
|
m_core->v__DOT__thecpu__DOT__opvalid,
|
m_core->v__DOT__thecpu__DOT__opvalid,
|
m_core->v__DOT__thecpu__DOT__op_gie,
|
m_core->v__DOT__thecpu__DOT__op_gie,
|
m_core->v__DOT__thecpu__DOT__op_stall,
|
m_core->v__DOT__thecpu__DOT__op_stall,
|
m_core->v__DOT__thecpu__DOT__op_pc-1); ln++;
|
m_core->v__DOT__thecpu__DOT__op_pc-1); ln++;
|
|
|
showins(ln, "Al",
|
showins(ln, "Al",
|
m_core->v__DOT__thecpu__DOT__alu_ce,
|
m_core->v__DOT__thecpu__DOT__alu_ce,
|
m_core->v__DOT__thecpu__DOT__alu_pc_valid,
|
m_core->v__DOT__thecpu__DOT__alu_pc_valid,
|
m_core->v__DOT__thecpu__DOT__alu_gie,
|
m_core->v__DOT__thecpu__DOT__alu_gie,
|
m_core->v__DOT__thecpu__DOT__alu_stall,
|
m_core->v__DOT__thecpu__DOT__alu_stall,
|
m_core->v__DOT__thecpu__DOT__alu_pc-1); ln++;
|
m_core->v__DOT__thecpu__DOT__alu_pc-1); ln++;
|
}
|
}
|
void tick(void) {
|
void tick(void) {
|
int gie = m_core->v__DOT__thecpu__DOT__gie;
|
int gie = m_core->v__DOT__thecpu__DOT__gie;
|
/*
|
/*
|
m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
|
m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
|
m_core->o_qspi_sck,
|
m_core->o_qspi_sck,
|
m_core->o_qspi_dat);
|
m_core->o_qspi_dat);
|
*/
|
*/
|
|
|
int stb = m_core->o_wb_stb;
|
int stb = m_core->o_wb_stb;
|
if ((m_core->o_wb_addr & (-1<<20))!=1)
|
if ((m_core->o_wb_addr & (-1<<20))!=1)
|
stb = 0;
|
stb = 0;
|
m_mem(m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
|
m_mem(m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
|
m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
|
m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
|
m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
|
m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
|
if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb))
|
if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb))
|
m_core->i_wb_ack = 1;
|
m_core->i_wb_ack = 1;
|
|
|
if ((dbg_flag)&&(dbg_fp)) {
|
if ((dbg_flag)&&(dbg_fp)) {
|
fprintf(dbg_fp, "DBG %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s\n",
|
fprintf(dbg_fp, "DBG %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s\n",
|
(m_core->i_dbg_cyc)?"CYC":" ",
|
(m_core->i_dbg_cyc)?"CYC":" ",
|
(m_core->i_dbg_stb)?"STB":
|
(m_core->i_dbg_stb)?"STB":
|
((m_core->v__DOT__dbg_stb)?"DBG":" "),
|
((m_core->v__DOT__dbg_stb)?"DBG":" "),
|
((m_core->i_dbg_we)?"WE":" "),
|
((m_core->i_dbg_we)?"WE":" "),
|
(m_core->i_dbg_addr),0,
|
(m_core->i_dbg_addr),0,
|
m_core->i_dbg_data,
|
m_core->i_dbg_data,
|
(m_core->o_dbg_ack)?"ACK":" ",
|
(m_core->o_dbg_ack)?"ACK":" ",
|
(m_core->o_dbg_stall)?"STALL":" ",
|
(m_core->o_dbg_stall)?"STALL":" ",
|
(m_core->o_dbg_data),
|
(m_core->o_dbg_data),
|
(m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
|
(m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
|
(m_core->v__DOT__cpu_dbg_stall)?"CPU-DBG_STALL":"",
|
(m_core->v__DOT__cpu_dbg_stall)?"CPU-DBG_STALL":"",
|
(m_core->v__DOT__thecpu__DOT__dcdvalid)?"DCDV ":"",
|
(m_core->v__DOT__thecpu__DOT__dcdvalid)?"DCDV ":"",
|
(m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
|
(m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
|
(m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
|
(m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
|
(m_core->v__DOT__thecpu__DOT__mem_cyc)?"MCYC ":"",
|
(m_core->v__DOT__thecpu__DOT__mem_cyc)?"MCYC ":"",
|
(m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
|
(m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
|
(m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"",
|
(m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"",
|
(m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"",
|
(m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"",
|
(m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV ":"");
|
(m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV ":"");
|
fprintf(dbg_fp, " SYS %s %s %s @0x%08x/%d[0x%08x] %s [0x%08x]\n",
|
fprintf(dbg_fp, " SYS %s %s %s @0x%08x/%d[0x%08x] %s [0x%08x]\n",
|
(m_core->v__DOT__sys_cyc)?"CYC":" ",
|
(m_core->v__DOT__sys_cyc)?"CYC":" ",
|
(m_core->v__DOT__sys_stb)?"STB":" ",
|
(m_core->v__DOT__sys_stb)?"STB":" ",
|
(m_core->v__DOT__sys_we)?"WE":" ",
|
(m_core->v__DOT__sys_we)?"WE":" ",
|
(m_core->v__DOT__sys_addr),
|
(m_core->v__DOT__sys_addr),
|
(m_core->v__DOT__dbg_addr),
|
(m_core->v__DOT__dbg_addr),
|
(m_core->v__DOT__sys_data),
|
(m_core->v__DOT__sys_data),
|
(m_core->v__DOT__dbg_ack)?"ACK":" ",
|
(m_core->v__DOT__dbg_ack)?"ACK":" ",
|
(m_core->v__DOT__wb_data));
|
(m_core->v__DOT__wb_data));
|
}
|
}
|
|
|
if (dbg_fp)
|
if (dbg_fp)
|
fprintf(dbg_fp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d,%d ce=%d, valid=%d, wr=%d Reg=%02x, IPC=%08x, UPC=%08x\n",
|
fprintf(dbg_fp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d,%d ce=%d, valid=%d, wr=%d Reg=%02x, IPC=%08x, UPC=%08x\n",
|
m_core->v__DOT__thecpu__DOT__dcd_ce,
|
m_core->v__DOT__thecpu__DOT__dcd_ce,
|
m_core->v__DOT__thecpu__DOT__dcd_pc,
|
m_core->v__DOT__thecpu__DOT__dcd_pc,
|
m_core->v__DOT__thecpu__DOT__op_ce,
|
m_core->v__DOT__thecpu__DOT__op_ce,
|
m_core->v__DOT__thecpu__DOT__op_pc,
|
m_core->v__DOT__thecpu__DOT__op_pc,
|
m_core->v__DOT__thecpu__DOT__dcdA,
|
m_core->v__DOT__thecpu__DOT__dcdA,
|
m_core->v__DOT__thecpu__DOT__opR,
|
m_core->v__DOT__thecpu__DOT__opR,
|
m_core->v__DOT__cmd_halt,
|
m_core->v__DOT__cmd_halt,
|
m_core->v__DOT__cpu_halt,
|
m_core->v__DOT__cpu_halt,
|
m_core->v__DOT__thecpu__DOT__alu_ce,
|
m_core->v__DOT__thecpu__DOT__alu_ce,
|
m_core->v__DOT__thecpu__DOT__alu_valid,
|
m_core->v__DOT__thecpu__DOT__alu_valid,
|
m_core->v__DOT__thecpu__DOT__alu_wr,
|
m_core->v__DOT__thecpu__DOT__alu_wr,
|
m_core->v__DOT__thecpu__DOT__alu_reg,
|
m_core->v__DOT__thecpu__DOT__alu_reg,
|
m_core->v__DOT__thecpu__DOT__ipc,
|
m_core->v__DOT__thecpu__DOT__ipc,
|
m_core->v__DOT__thecpu__DOT__upc);
|
m_core->v__DOT__thecpu__DOT__upc);
|
|
|
if ((dbg_fp)&&(!gie)&&(m_core->v__DOT__thecpu__DOT__w_release_from_interrupt)) {
|
if ((dbg_fp)&&(!gie)&&(m_core->v__DOT__thecpu__DOT__w_release_from_interrupt)) {
|
fprintf(dbg_fp, "RELEASE: int=%d, %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d\n",
|
fprintf(dbg_fp, "RELEASE: int=%d, %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d\n",
|
m_core->v__DOT__pic_interrupt,
|
m_core->v__DOT__pic_interrupt,
|
m_core->v__DOT__thecpu__DOT__wr_reg_ce,
|
m_core->v__DOT__thecpu__DOT__wr_reg_ce,
|
m_core->v__DOT__thecpu__DOT__wr_reg_id,
|
m_core->v__DOT__thecpu__DOT__wr_reg_id,
|
m_core->v__DOT__thecpu__DOT__wr_reg_vl,
|
m_core->v__DOT__thecpu__DOT__wr_reg_vl,
|
m_core->v__DOT__cmd_addr,
|
m_core->v__DOT__cmd_addr,
|
m_core->v__DOT__dbg_idata,
|
m_core->v__DOT__dbg_idata,
|
m_core->v__DOT__thecpu__DOT__master_ce,
|
m_core->v__DOT__thecpu__DOT__master_ce,
|
m_core->v__DOT__thecpu__DOT__alu_wr,
|
m_core->v__DOT__thecpu__DOT__alu_wr,
|
m_core->v__DOT__thecpu__DOT__alu_valid,
|
m_core->v__DOT__thecpu__DOT__alu_valid,
|
m_core->v__DOT__thecpu__DOT__mem_valid);
|
m_core->v__DOT__thecpu__DOT__mem_valid);
|
} else if ((dbg_fp)&&(gie)&&(m_core->v__DOT__thecpu__DOT__w_switch_to_interrupt)) {
|
} else if ((dbg_fp)&&(gie)&&(m_core->v__DOT__thecpu__DOT__w_switch_to_interrupt)) {
|
fprintf(dbg_fp, "SWITCH: %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d, F%02x,%02x\n",
|
fprintf(dbg_fp, "SWITCH: %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d, F%02x,%02x\n",
|
m_core->v__DOT__thecpu__DOT__wr_reg_ce,
|
m_core->v__DOT__thecpu__DOT__wr_reg_ce,
|
m_core->v__DOT__thecpu__DOT__wr_reg_id,
|
m_core->v__DOT__thecpu__DOT__wr_reg_id,
|
m_core->v__DOT__thecpu__DOT__wr_reg_vl,
|
m_core->v__DOT__thecpu__DOT__wr_reg_vl,
|
m_core->v__DOT__cmd_addr,
|
m_core->v__DOT__cmd_addr,
|
m_core->v__DOT__dbg_idata,
|
m_core->v__DOT__dbg_idata,
|
m_core->v__DOT__thecpu__DOT__master_ce,
|
m_core->v__DOT__thecpu__DOT__master_ce,
|
m_core->v__DOT__thecpu__DOT__alu_wr,
|
m_core->v__DOT__thecpu__DOT__alu_wr,
|
m_core->v__DOT__thecpu__DOT__alu_valid,
|
m_core->v__DOT__thecpu__DOT__alu_valid,
|
m_core->v__DOT__thecpu__DOT__mem_valid,
|
m_core->v__DOT__thecpu__DOT__mem_valid,
|
m_core->v__DOT__thecpu__DOT__w_iflags,
|
m_core->v__DOT__thecpu__DOT__w_iflags,
|
m_core->v__DOT__thecpu__DOT__w_uflags);
|
m_core->v__DOT__thecpu__DOT__w_uflags);
|
fprintf(dbg_fp, "\tbrk=%d,%d\n",
|
fprintf(dbg_fp, "\tbrk=%d,%d\n",
|
m_core->v__DOT__thecpu__DOT__break_en,
|
m_core->v__DOT__thecpu__DOT__break_en,
|
m_core->v__DOT__thecpu__DOT__op_break);
|
m_core->v__DOT__thecpu__DOT__op_break);
|
}
|
}
|
|
|
|
if (dbg_fp) {
|
|
if(m_core->v__DOT__thecpu__DOT__clear_pipeline)
|
|
fprintf(dbg_fp, "\tClear Pipeline\n");
|
|
if(m_core->v__DOT__thecpu__DOT__new_pc)
|
|
fprintf(dbg_fp, "\tNew PC\n");
|
|
}
|
|
|
TESTB<Vzipsystem>::tick();
|
TESTB<Vzipsystem>::tick();
|
if ((dbg_fp)&&(gie != m_core->v__DOT__thecpu__DOT__gie)) {
|
if ((dbg_fp)&&(gie != m_core->v__DOT__thecpu__DOT__gie)) {
|
fprintf(dbg_fp, "SWITCH FROM %s to %s: sPC = 0x%08x uPC = 0x%08x pf_pc = 0x%08x\n",
|
fprintf(dbg_fp, "SWITCH FROM %s to %s: sPC = 0x%08x uPC = 0x%08x pf_pc = 0x%08x\n",
|
(gie)?"User":"Supervisor",
|
(gie)?"User":"Supervisor",
|
(gie)?"Supervisor":"User",
|
(gie)?"Supervisor":"User",
|
m_core->v__DOT__thecpu__DOT__ipc,
|
m_core->v__DOT__thecpu__DOT__ipc,
|
m_core->v__DOT__thecpu__DOT__upc,
|
m_core->v__DOT__thecpu__DOT__upc,
|
m_core->v__DOT__thecpu__DOT__pf_pc);
|
m_core->v__DOT__thecpu__DOT__pf_pc);
|
} if (dbg_fp) {
|
} if (dbg_fp) {
|
dbgins("Op - ", m_core->v__DOT__thecpu__DOT__op_ce,
|
dbgins("Op - ", m_core->v__DOT__thecpu__DOT__op_ce,
|
m_core->v__DOT__thecpu__DOT__opvalid,
|
m_core->v__DOT__thecpu__DOT__opvalid,
|
m_core->v__DOT__thecpu__DOT__op_gie,
|
m_core->v__DOT__thecpu__DOT__op_gie,
|
m_core->v__DOT__thecpu__DOT__op_stall,
|
m_core->v__DOT__thecpu__DOT__op_stall,
|
m_core->v__DOT__thecpu__DOT__op_pc-1);
|
m_core->v__DOT__thecpu__DOT__op_pc-1);
|
dbgins("Al - ",
|
dbgins("Al - ",
|
m_core->v__DOT__thecpu__DOT__alu_ce,
|
m_core->v__DOT__thecpu__DOT__alu_ce,
|
m_core->v__DOT__thecpu__DOT__alu_pc_valid,
|
m_core->v__DOT__thecpu__DOT__alu_pc_valid,
|
m_core->v__DOT__thecpu__DOT__alu_gie,
|
m_core->v__DOT__thecpu__DOT__alu_gie,
|
m_core->v__DOT__thecpu__DOT__alu_stall,
|
m_core->v__DOT__thecpu__DOT__alu_stall,
|
m_core->v__DOT__thecpu__DOT__alu_pc-1);
|
m_core->v__DOT__thecpu__DOT__alu_pc-1);
|
|
|
}
|
}
|
}
|
}
|
|
|
bool test_success(void) {
|
bool test_success(void) {
|
return ((!m_core->v__DOT__thecpu__DOT__gie)
|
return ((!m_core->v__DOT__thecpu__DOT__gie)
|
&&(m_core->v__DOT__thecpu__DOT__sleep));
|
&&(m_core->v__DOT__thecpu__DOT__sleep));
|
}
|
}
|
|
|
bool test_failure(void) {
|
bool test_failure(void) {
|
return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
|
return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
|
&&(m_mem[m_core->v__DOT__thecpu__DOT__alu_pc-1]
|
&&(m_mem[m_core->v__DOT__thecpu__DOT__alu_pc-1]
|
== 0x2f0f7fff));
|
== 0x2f0f7fff));
|
}
|
}
|
|
|
void wb_write(unsigned a, unsigned int v) {
|
void wb_write(unsigned a, unsigned int v) {
|
mvprintw(0,35, "%40s", "");
|
mvprintw(0,35, "%40s", "");
|
mvprintw(0,40, "wb_write(%d,%x)", a, v);
|
mvprintw(0,40, "wb_write(%d,%x)", a, v);
|
m_core->i_dbg_cyc = 1;
|
m_core->i_dbg_cyc = 1;
|
m_core->i_dbg_stb = 1;
|
m_core->i_dbg_stb = 1;
|
m_core->i_dbg_we = 1;
|
m_core->i_dbg_we = 1;
|
m_core->i_dbg_addr = a & 1;
|
m_core->i_dbg_addr = a & 1;
|
m_core->i_dbg_data = v;
|
m_core->i_dbg_data = v;
|
|
|
tick();
|
tick();
|
while(m_core->o_dbg_stall)
|
while(m_core->o_dbg_stall)
|
tick();
|
tick();
|
|
|
m_core->i_dbg_stb = 0;
|
m_core->i_dbg_stb = 0;
|
while(!m_core->o_dbg_ack)
|
while(!m_core->o_dbg_ack)
|
tick();
|
tick();
|
|
|
// Release the bus
|
// Release the bus
|
m_core->i_dbg_cyc = 0;
|
m_core->i_dbg_cyc = 0;
|
m_core->i_dbg_stb = 0;
|
m_core->i_dbg_stb = 0;
|
tick();
|
tick();
|
mvprintw(0,35, "%40s", "");
|
mvprintw(0,35, "%40s", "");
|
mvprintw(0,40, "wb_write -- complete");
|
mvprintw(0,40, "wb_write -- complete");
|
}
|
}
|
|
|
unsigned long wb_read(unsigned a) {
|
unsigned long wb_read(unsigned a) {
|
unsigned int v;
|
unsigned int v;
|
mvprintw(0,35, "%40s", "");
|
mvprintw(0,35, "%40s", "");
|
mvprintw(0,40, "wb_read(0x%08x)", a);
|
mvprintw(0,40, "wb_read(0x%08x)", a);
|
m_core->i_dbg_cyc = 1;
|
m_core->i_dbg_cyc = 1;
|
m_core->i_dbg_stb = 1;
|
m_core->i_dbg_stb = 1;
|
m_core->i_dbg_we = 0;
|
m_core->i_dbg_we = 0;
|
m_core->i_dbg_addr = a & 1;
|
m_core->i_dbg_addr = a & 1;
|
|
|
tick();
|
tick();
|
while(m_core->o_dbg_stall)
|
while(m_core->o_dbg_stall)
|
tick();
|
tick();
|
|
|
m_core->i_dbg_stb = 0;
|
m_core->i_dbg_stb = 0;
|
while(!m_core->o_dbg_ack)
|
while(!m_core->o_dbg_ack)
|
tick();
|
tick();
|
v = m_core->o_dbg_data;
|
v = m_core->o_dbg_data;
|
|
|
// Release the bus
|
// Release the bus
|
m_core->i_dbg_cyc = 0;
|
m_core->i_dbg_cyc = 0;
|
m_core->i_dbg_stb = 0;
|
m_core->i_dbg_stb = 0;
|
tick();
|
tick();
|
|
|
mvprintw(0,35, "%40s", "");
|
mvprintw(0,35, "%40s", "");
|
mvprintw(0,40, "wb_read = 0x%08x", v);
|
mvprintw(0,40, "wb_read = 0x%08x", v);
|
|
|
return v;
|
return v;
|
}
|
}
|
|
|
|
void cursor_up(void) {
|
|
if (m_cursor > 3)
|
|
m_cursor -= 4;
|
|
} void cursor_down(void) {
|
|
if (m_cursor < 40)
|
|
m_cursor += 4;
|
|
} void cursor_left(void) {
|
|
if (m_cursor > 0)
|
|
m_cursor--;
|
|
else m_cursor = 43;
|
|
} void cursor_right(void) {
|
|
if (m_cursor < 43)
|
|
m_cursor++;
|
|
else m_cursor = 0;
|
|
}
|
|
|
|
int cursor(void) { return m_cursor; }
|
};
|
};
|
|
|
|
void get_value(ZIPPY_TB *tb) {
|
|
int wy, wx, ra;
|
|
int c = tb->cursor();
|
|
|
|
wx = (c & 0x03) * 20 + 9;
|
|
wy = (c>>2);
|
|
if (wy >= 3+4)
|
|
wy++;
|
|
if (wy > 3)
|
|
wy += 2;
|
|
wy++;
|
|
|
|
if (c >= 12)
|
|
ra = c - 12;
|
|
else
|
|
ra = c + 32;
|
|
|
|
bool done = false;
|
|
char str[16];
|
|
int pos = 0; str[pos] = '\0';
|
|
while(!done) {
|
|
int chv = getch();
|
|
switch(chv) {
|
|
case KEY_ESCAPE:
|
|
pos = 0; str[pos] = '\0'; done = true;
|
|
break;
|
|
case KEY_RETURN: case KEY_ENTER: case KEY_UP: case KEY_DOWN:
|
|
done = true;
|
|
break;
|
|
case KEY_LEFT: case KEY_BACKSPACE:
|
|
if (pos > 0) pos--;
|
|
break;
|
|
case KEY_CLEAR:
|
|
pos = 0;
|
|
break;
|
|
case '0': case ' ': str[pos++] = '0'; break;
|
|
case '1': str[pos++] = '1'; break;
|
|
case '2': str[pos++] = '2'; break;
|
|
case '3': str[pos++] = '3'; break;
|
|
case '4': str[pos++] = '4'; break;
|
|
case '5': str[pos++] = '5'; break;
|
|
case '6': str[pos++] = '6'; break;
|
|
case '7': str[pos++] = '7'; break;
|
|
case '8': str[pos++] = '8'; break;
|
|
case '9': str[pos++] = '9'; break;
|
|
case 'A': case 'a': str[pos++] = 'A'; break;
|
|
case 'B': case 'b': str[pos++] = 'B'; break;
|
|
case 'C': case 'c': str[pos++] = 'C'; break;
|
|
case 'D': case 'd': str[pos++] = 'D'; break;
|
|
case 'E': case 'e': str[pos++] = 'E'; break;
|
|
case 'F': case 'f': str[pos++] = 'F'; break;
|
|
}
|
|
|
|
if (pos > 8)
|
|
pos = 8;
|
|
str[pos] = '\0';
|
|
|
|
attron(A_NORMAL | A_UNDERLINE);
|
|
mvprintw(wy, wx, "%-8s", str);
|
|
if (pos > 0) {
|
|
attron(A_NORMAL | A_UNDERLINE | A_BLINK);
|
|
mvprintw(wy, wx+pos-1, "%c", str[pos-1]);
|
|
}
|
|
attrset(A_NORMAL);
|
|
}
|
|
|
|
if (pos > 0) {
|
|
int v;
|
|
v = strtoul(str, NULL, 16);
|
|
if (!tb->halted()) {
|
|
switch(ra) {
|
|
case 15:
|
|
tb->m_core->v__DOT__thecpu__DOT__ipc = v;
|
|
if (!tb->m_core->v__DOT__thecpu__DOT__gie) {
|
|
tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
|
|
tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
|
|
tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
|
|
tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
|
|
tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
|
|
tb->m_core->v__DOT__thecpu__DOT__dcdvalid = 0;
|
|
tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
|
|
}
|
|
break;
|
|
case 31:
|
|
tb->m_core->v__DOT__thecpu__DOT__upc = v;
|
|
if (tb->m_core->v__DOT__thecpu__DOT__gie) {
|
|
tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
|
|
tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
|
|
tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
|
|
tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
|
|
tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
|
|
tb->m_core->v__DOT__thecpu__DOT__dcdvalid = 0;
|
|
tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
|
|
}
|
|
break;
|
|
case 32: tb->m_core->v__DOT__pic_data = v; break;
|
|
case 33: tb->m_core->v__DOT__watchdog__DOT__r_value = v; break;
|
|
case 34: tb->m_core->v__DOT__manualcache__DOT__cache_base = v; break;
|
|
case 35: tb->m_core->v__DOT__ctri__DOT__r_int_state = v; break;
|
|
case 36: tb->m_core->v__DOT__timer_a__DOT__r_value = v; break;
|
|
case 37: tb->m_core->v__DOT__timer_b__DOT__r_value = v; break;
|
|
case 38: tb->m_core->v__DOT__timer_c__DOT__r_value = v; break;
|
|
case 39: tb->m_core->v__DOT__jiffies__DOT__r_counter = v; break;
|
|
case 44: tb->m_core->v__DOT__utc_data = v; break;
|
|
case 45: tb->m_core->v__DOT__uoc_data = v; break;
|
|
case 46: tb->m_core->v__DOT__upc_data = v; break;
|
|
case 47: tb->m_core->v__DOT__uic_data = v; break;
|
|
default:
|
|
tb->m_core->v__DOT__thecpu__DOT__regset[ra] = v;
|
|
break;
|
|
}
|
|
} else
|
|
tb->cmd_write(ra, v);
|
|
}
|
|
}
|
|
|
void usage(void) {
|
void usage(void) {
|
printf("USAGE: zippy_tb [-a] <testfile.out>\n");
|
printf("USAGE: zippy_tb [-a] <testfile.out>\n");
|
printf("\n");
|
printf("\n");
|
printf("\tWhere testfile.out is an output file from the assembler.\n");
|
printf("\tWhere testfile.out is an output file from the assembler.\n");
|
printf("\t-a\tSets the testbench to run automatically without any\n");
|
printf("\t-a\tSets the testbench to run automatically without any\n");
|
printf("\t\tuser interaction.\n");
|
printf("\t\tuser interaction.\n");
|
printf("\n");
|
printf("\n");
|
printf("\tUser Commands:\n");
|
printf("\tUser Commands:\n");
|
printf("\t\tWhen the test bench is run interactively, the following\n");
|
printf("\t\tWhen the test bench is run interactively, the following\n");
|
printf("\t\tkey strokes are recognized:\n");
|
printf("\t\tkey strokes are recognized:\n");
|
printf("\t\t\'h\'\tHalt the processor using the external interface.\n");
|
printf("\t\t\'h\'\tHalt the processor using the external interface.\n");
|
printf("\t\t\'g\'\tLet the processor run at full throttle with no.\n");
|
printf("\t\t\'g\'\tLet the processor run at full throttle with no.\n");
|
printf("\t\t\tuser intervention.\n");
|
printf("\t\t\tuser intervention.\n");
|
printf("\t\t\'q\'\tQuit the simulation.\n");
|
printf("\t\t\'q\'\tQuit the simulation.\n");
|
printf("\t\t\'r\'\tReset the processor.\n");
|
printf("\t\t\'r\'\tReset the processor.\n");
|
printf("\t\t\'s\'\tStep the CPU using the external stepping command\n");
|
printf("\t\t\'s\'\tStep the CPU using the external stepping command\n");
|
printf("\t\t\tThis may consume more than one tick.\n");
|
printf("\t\t\tThis may consume more than one tick.\n");
|
printf("\t\t\'t\'\tClock a single tick through the system.\n");
|
printf("\t\t\'t\'\tClock a single tick through the system.\n");
|
}
|
}
|
|
|
int main(int argc, char **argv) {
|
int main(int argc, char **argv) {
|
Verilated::commandArgs(argc, argv);
|
Verilated::commandArgs(argc, argv);
|
ZIPPY_TB *tb = new ZIPPY_TB();
|
ZIPPY_TB *tb = new ZIPPY_TB();
|
bool autorun = false, exit_on_done = false;
|
bool autorun = false, exit_on_done = false;
|
|
|
// mem[0x00000] = 0xbe000010; // Halt instruction
|
// mem[0x00000] = 0xbe000010; // Halt instruction
|
unsigned int mptr = 0;
|
unsigned int mptr = 0;
|
|
|
if (argc <= 1) {
|
if (argc <= 1) {
|
usage();
|
usage();
|
exit(-1);
|
exit(-1);
|
} else {
|
} else {
|
for(int argn=1; argn<argc; argn++) {
|
for(int argn=1; argn<argc; argn++) {
|
if (argv[argn][0] == '-') {
|
if (argv[argn][0] == '-') {
|
switch(argv[argn][1]) {
|
switch(argv[argn][1]) {
|
case 'a':
|
case 'a':
|
autorun = true;
|
autorun = true;
|
break;
|
break;
|
case 'e':
|
case 'e':
|
exit_on_done = true;
|
exit_on_done = true;
|
break;
|
break;
|
case 'h':
|
case 'h':
|
usage();
|
usage();
|
exit(0);
|
exit(0);
|
break;
|
break;
|
default:
|
default:
|
usage();
|
usage();
|
exit(-1);
|
exit(-1);
|
break;
|
break;
|
}
|
}
|
} else if (access(argv[argn], R_OK)==0) {
|
} else if (access(argv[argn], R_OK)==0) {
|
FILE *fp = fopen(argv[argn], "r");
|
FILE *fp = fopen(argv[argn], "r");
|
if (fp == NULL) {
|
if (fp == NULL) {
|
printf("Cannot open %s\n", argv[argn]);
|
printf("Cannot open %s\n", argv[argn]);
|
perror("O/S Err: ");
|
perror("O/S Err: ");
|
exit(-1);
|
exit(-1);
|
} mptr += fread(&tb->m_mem[mptr], sizeof(ZIPI), tb->m_mem_size - mptr, fp);
|
} mptr += fread(&tb->m_mem[mptr], sizeof(ZIPI), tb->m_mem_size - mptr, fp);
|
fclose(fp);
|
fclose(fp);
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
if (autorun) {
|
if (autorun) {
|
bool done = false;
|
bool done = false;
|
|
|
printf("Running in non-interactive mode\n");
|
printf("Running in non-interactive mode\n");
|
tb->reset();
|
tb->reset();
|
for(int i=0; i<2; i++)
|
for(int i=0; i<2; i++)
|
tb->tick();
|
tb->tick();
|
tb->m_core->v__DOT__cmd_halt = 0;
|
tb->m_core->v__DOT__cmd_halt = 0;
|
while(!done) {
|
while(!done) {
|
tb->tick();
|
tb->tick();
|
|
|
// tb->m_core->v__DOT__thecpu__DOT__step = 0;
|
// tb->m_core->v__DOT__thecpu__DOT__step = 0;
|
// tb->m_core->v__DOT__cmd_halt = 0;
|
// tb->m_core->v__DOT__cmd_halt = 0;
|
// tb->m_core->v__DOT__cmd_step = 0;
|
// tb->m_core->v__DOT__cmd_step = 0;
|
|
|
printf("PC = %08x:%08x (%08x)\n",
|
/*
|
tb->m_core->v__DOT__thecpu__DOT__ipc,
|
printf("PC = %08x:%08x (%08x)\n",
|
tb->m_core->v__DOT__thecpu__DOT__upc,
|
tb->m_core->v__DOT__thecpu__DOT__ipc,
|
tb->m_core->v__DOT__thecpu__DOT__alu_pc);
|
tb->m_core->v__DOT__thecpu__DOT__upc,
|
|
tb->m_core->v__DOT__thecpu__DOT__alu_pc);
|
|
*/
|
|
|
done = (tb->test_success())||(tb->test_failure());
|
done = (tb->test_success())||(tb->test_failure());
|
}
|
}
|
} else { // Interactive
|
} else { // Interactive
|
initscr();
|
initscr();
|
raw();
|
raw();
|
noecho();
|
noecho();
|
keypad(stdscr, true);
|
keypad(stdscr, true);
|
|
|
tb->reset();
|
tb->reset();
|
for(int i=0; i<2; i++)
|
for(int i=0; i<2; i++)
|
tb->tick();
|
tb->tick();
|
tb->m_core->v__DOT__cmd_halt = 0;
|
tb->m_core->v__DOT__cmd_halt = 0;
|
|
|
int chv = 'q';
|
int chv = 'q';
|
|
|
bool done = false, halted = true, manual = true;
|
bool done = false, halted = true, manual = true;
|
|
|
halfdelay(1);
|
halfdelay(1);
|
// tb->wb_write(CMD_REG, CMD_HALT | CMD_RESET);
|
// tb->wb_write(CMD_REG, CMD_HALT | CMD_RESET);
|
// while((tb->wb_read(CMD_REG) & (CMD_HALT|CMD_STALL))==(CMD_HALT|CMD_STALL))
|
// while((tb->wb_read(CMD_REG) & (CMD_HALT|CMD_STALL))==(CMD_HALT|CMD_STALL))
|
// tb->show_state();
|
// tb->show_state();
|
|
|
while(!done) {
|
while(!done) {
|
chv = getch();
|
chv = getch();
|
switch(chv) {
|
switch(chv) {
|
case 'h': case 'H':
|
case 'h': case 'H':
|
tb->wb_write(CMD_REG, CMD_HALT);
|
tb->wb_write(CMD_REG, CMD_HALT);
|
if (!halted)
|
if (!halted)
|
erase();
|
erase();
|
halted = true;
|
halted = true;
|
break;
|
break;
|
case 'g': case 'G':
|
case 'g': case 'G':
|
tb->wb_write(CMD_REG, 0);
|
tb->wb_write(CMD_REG, 0);
|
if (halted)
|
if (halted)
|
erase();
|
erase();
|
halted = false;
|
halted = false;
|
manual = false;
|
manual = false;
|
break;
|
break;
|
case 'q': case 'Q':
|
case 'q': case 'Q':
|
done = true;
|
done = true;
|
break;
|
break;
|
case 'r': case 'R':
|
case 'r': case 'R':
|
tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
|
tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
|
halted = true;
|
halted = true;
|
erase();
|
erase();
|
break;
|
break;
|
case 's': case 'S':
|
case 's': case 'S':
|
if (manual)
|
if (!halted)
|
erase();
|
erase();
|
tb->wb_write(CMD_REG, CMD_STEP);
|
tb->wb_write(CMD_REG, CMD_STEP);
|
manual = false;
|
manual = false;
|
|
halted = true;
|
break;
|
break;
|
case 't': case 'T':
|
case 't': case 'T':
|
if (!manual)
|
if ((!manual)||(halted))
|
erase();
|
erase();
|
manual = true;
|
manual = true;
|
|
halted = false;
|
// tb->m_core->v__DOT__thecpu__DOT__step = 0;
|
// tb->m_core->v__DOT__thecpu__DOT__step = 0;
|
// tb->m_core->v__DOT__cmd_halt = 0;
|
// tb->m_core->v__DOT__cmd_halt = 0;
|
// tb->m_core->v__DOT__cmd_step = 0;
|
// tb->m_core->v__DOT__cmd_step = 0;
|
tb->tick();
|
tb->tick();
|
break;
|
break;
|
case ERR:
|
case KEY_IC: case KEY_ENTER: case KEY_RETURN:
|
|
get_value(tb);
|
|
break;
|
|
case KEY_UP: tb->cursor_up(); break;
|
|
case KEY_DOWN: tb->cursor_down(); break;
|
|
case KEY_LEFT: tb->cursor_left(); break;
|
|
case KEY_RIGHT: tb->cursor_right(); break;
|
|
case ERR: case KEY_CLEAR:
|
default:
|
default:
|
if (!manual)
|
if (!manual)
|
tb->tick();
|
tb->tick();
|
}
|
}
|
|
|
if (manual) {
|
if (manual) {
|
tb->show_state();
|
tb->show_state();
|
} else if (halted) {
|
} else if (halted) {
|
if (tb->dbg_fp)
|
if (tb->dbg_fp)
|
fprintf(tb->dbg_fp, "\n\nREAD-STATE ******\n");
|
fprintf(tb->dbg_fp, "\n\nREAD-STATE ******\n");
|
tb->read_state();
|
tb->read_state();
|
} else
|
} else
|
tb->show_state();
|
tb->show_state();
|
|
|
if (tb->m_core->i_rst)
|
if (tb->m_core->i_rst)
|
done =true;
|
done =true;
|
if (tb->bomb)
|
if (tb->bomb)
|
done = true;
|
done = true;
|
|
|
if (exit_on_done) {
|
if (exit_on_done) {
|
if (tb->test_success())
|
if (tb->test_success())
|
done = true;
|
done = true;
|
if (tb->test_failure())
|
if (tb->test_failure())
|
done = true;
|
done = true;
|
}
|
}
|
}
|
}
|
endwin();
|
endwin();
|
}
|
}
|
#ifdef MANUAL_STEPPING_MODE
|
#ifdef MANUAL_STEPPING_MODE
|
else { // Manual stepping mode
|
else { // Manual stepping mode
|
tb->show_state();
|
tb->show_state();
|
|
|
while('q' != tolower(chv = getch())) {
|
while('q' != tolower(chv = getch())) {
|
tb->tick();
|
tb->tick();
|
tb->show_state();
|
tb->show_state();
|
|
|
if (tb->test_success())
|
if (tb->test_success())
|
break;
|
break;
|
else if (tb->test_failure())
|
else if (tb->test_failure())
|
break;
|
break;
|
}
|
}
|
}
|
}
|
#endif
|
#endif
|
|
|
printf("Clocks used : %08x\n", tb->m_core->v__DOT__mtc_data);
|
printf("Clocks used : %08x\n", tb->m_core->v__DOT__mtc_data);
|
printf("Instructions Issued : %08x\n", tb->m_core->v__DOT__mic_data);
|
printf("Instructions Issued : %08x\n", tb->m_core->v__DOT__mic_data);
|
if (tb->m_core->v__DOT__mtc_data != 0)
|
if (tb->m_core->v__DOT__mtc_data != 0)
|
printf("Instructions / Clock: %.2f\n",
|
printf("Instructions / Clock: %.2f\n",
|
(double)tb->m_core->v__DOT__mic_data
|
(double)tb->m_core->v__DOT__mic_data
|
/ (double)tb->m_core->v__DOT__mtc_data);
|
/ (double)tb->m_core->v__DOT__mtc_data);
|
if (tb->test_success())
|
if (tb->test_success())
|
printf("SUCCESS!\n");
|
printf("SUCCESS!\n");
|
else if (tb->test_failure())
|
else if (tb->test_failure())
|
printf("TEST FAILED!\n");
|
printf("TEST FAILED!\n");
|
else
|
else
|
printf("User quit\n");
|
printf("User quit\n");
|
exit(0);
|
exit(0);
|
}
|
}
|
|
|
|
|
